0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization

Tuan, Anh; Lee, Zhao Chuan; Wang, Bo; Chang, Ik-Joon; Liu, Xin; Kim, Tony Tae-Hyoung

doi:10.1109/jssc.2016.2540799

Cited by 21 publications

(5 citation statements)

References 29 publications

(34 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is noteworthy that SRAM is placed in the regulated low-voltage domain for lower energy consumption. Considering the read failure problem of conventional 6T-SRAM at low voltages [32][33][34], a customized stable 7T-SRAM with error detection capability suited to EDaC systems was used.…”

Section: Ultra-low Voltage Implementationmentioning

confidence: 99%

Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller

Yu,

Li,

Deng

et al. 2023

Sensors

View full text Add to dashboard Cite

This paper presents an innovative approach for predicting timing errors tailored to near-/sub-threshold operations, addressing the energy-efficient requirements of digital circuits in applications, such as IoT devices and wearables. The method involves assessing deep path activity within an adjustable window prior to the root clock’s rising edge. By dynamically adapting the prediction window and supply voltage based on error detection outcomes, the approach effectively mitigates false predictions—an essential concern in low-voltage prediction techniques. The efficacy of this strategy is demonstrated through its implementation in a near-/sub-threshold 32-bit microprocessor system. The approach incurs only a modest 6.84% area overhead attributed to well-engineered lightweight design methodologies. Furthermore, with the integration of clock gating, the system functions seamlessly across a voltage range of 0.4 V–1.2 V (5–100 MHz), effectively catering to adaptive energy efficiency. Empirical results highlight the potential of the proposed strategy, achieving a significant 46.95% energy reduction at the Minimum Energy Point (MEP, 15 MHz) compared to signoff margins. Additionally, a 19.75% energy decrease is observed compared to the zero-margin operation, demonstrating successful realization of negative margins.

show abstract

Section: Ultra-low Voltage Implementationmentioning

confidence: 99%

Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller

Yu,

Li,

Deng

et al. 2023

Sensors

View full text Add to dashboard Cite

show abstract

“…SRAM dominates total chip power especially leakage power, thus the low leakage SRAM is urgently needed [2]. Near and sub-threshold SRAM is effective to reduce power dissipation, so they are extensively used in low power applications [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15].…”

Section: Introductionmentioning

confidence: 99%

“…Near and sub-threshold SRAM is effective to reduce power dissipation, so they are extensively used in low power applications [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]. 8T SRAM cell has taken the place of 6T cell to be a popular choice for the near and sub-threshold operation [2,3,4,5,6,7]. Unfortunately, 8T cell has additional leakage path compared to 6T cell, thus increasing the cell leakage [8].…”

Section: Introductionmentioning

confidence: 99%

A PMOS read-port 8T SRAM cell with optimized leakage power and enhanced performance

Cai

Jia

Chen

et al. 2017

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a novel PMOS read-port 8T SRAM cell, in which the read circuit is constructed by two cascaded PMOS transistors, and hence the leakage power is significantly optimized compared to the conventional 8T cell. Meanwhile, it also exhibits high area efficiency due to an equalized quantity of NMOS and PMOS transistors per cell. Furthermore, the proposed cell has sufficient potential to enhance performance by employing a Half-Schmitt inverter. The measurements indicate that the proposed cell outmatches conventional 8T cell in terms of leakage suppression and area saving, thus making it a superior choice for ultra low power applications.

show abstract

“…Many compensation techniques are proposed to address the PVT variation. The authors in [73] proposed a data randomization scheme for a subthreshold SRAM to reduce bitline swing degradation against PVT variations. In [74], the authors present a digital controller with static body-bias control generation schemes for an SRAM array and peripherals to optimize the leakage and improve the performance.…”

Section: The Effect Of Soft-errors In Subthreshold Sram Designmentioning

confidence: 99%

Ultra-Low Power and Reliable SRAM for Systems-on-Chip

Patel¹

View full text Add to dashboard Cite

The number of ubiquitous sensors has increased to more than double the human population and is expected to continue growing in the future. The pervasive use of sensors for applications such as personal healthcare and the Internet of Things (IoT) presents a growing sustainability challenge concerning the availability and accessibility of power sources. With 50 billion less BSN system. First, we explore different design knobs for an optimal SRAM design targeting ULP applications. These knobs include leveraging advanced fabrication technology, optimal device selection, circuit design techniques, and architectural techniques. Next, we evaluate the efficacy of different read and write peripheral assist techniques for improving reliability and energy efficiency of subthreshold SRAMs and provide stability, power, and performance trade-offs for system level optimization. The result of various optimization approaches resulted in a leakage and energy optimized SRAM operating over with leakage power reduced to 1.5 pW/bit while consuming only 6.24 pJ/access energy that is 40% more efficient than the previous version. To address a wide range of IoT applications with energy optimization, we propose a Canary sensor based minimum supply voltage (V M IN) tracking with optimal selection of the peripheral assist techniques. Later, we address the reliability issue at subthreshold operation using a process, voltage, and temperature (PVT) variation mitigation controller. Finally, the impact of the radiation-induced soft error is evaluated to provide a comprehensive study on reliability for the ULP SRAM at scaled V DD. Dedicating what all I learn in my life to 'Gurus' in my life-for enlightening my life with the knowledge, My Parents-for always giving me the courage to achieve impossible, My Wife-Pooja-for her unwavering love and motivation Meaning: Lead me from the unreal to the real; from darkness(ignorance) to light(knowledge); and from death to immortality. iv v Besides my life at the lab doing the research work, I immensely enjoyed my stay in Charlottesville. I am very much grateful to my neighbors for their pleasant company during my stay. I am also grateful to the members of Swadhyay Parivar for their selfless love. Last but never the least, I would like to thank my family members. I am very grateful for my parents, Naranbhai and Induben, for their continuous support and motivation for vii pursuing higher education. Especially, I thank my mother for always keeping me in her prayer while my father for giving me the courage to achieve whatever seems impossible to me. I thank my sister-Rinku-for her sisterly love. I cannot encompass my gratitude to my wife, Pooja, with the words for her support. She always been a lovely wife with continuous support. I am also indebted to almighty God for his blessing of two beautiful children, Samyak and Swara-my best stress busters! I cannot image myself completing my Ph.D. without the help of all these three-my wife and my kids-Thank you so much!

show abstract

0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization

Cited by 21 publications

References 29 publications

Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller

Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller

A PMOS read-port 8T SRAM cell with optimized leakage power and enhanced performance

Ultra-Low Power and Reliable SRAM for Systems-on-Chip

Contact Info

Product

Resources

About