Digital Distortion-Free PWM and Click Modulation

Self Cite

Summary In this paper, a novel pulse‐width modulator (PWM) for an all‐digital PWM transmitter based on switching amplification is presented. In this approach, each symbol is represented by a sequence of pre‐computed PWM pulse widths stored in a table that results in reduced error vector magnitude (EVM). A high‐resolution pulse former is then used to build the bipolar radio frequency (RF) signal. Simulations and comparisons to other approaches reported in the literature under different oversampling ratios and finite time resolutions are presented. The impact of nonlinearities in the variable duty‐cycle generator is also analyzed to demonstrate the robustness of the proposed technique.

“…Given an N ‐periodic discrete‐time signal

- 1 < \overset{v}{true} false[n false] < 1

with maximum frequency f C sampled at f pwm = N f C (with f C < f pwm /2) and defining

v false[n false] = false(1 + \overset{v}{true} false[n false] false) false/ 2

Section: Table‐based Proposed Approachmentioning

confidence: 99%

({, \begin{matrix} array \sum_{n = 0}^{N - 1} d_{L} [n] = N / 2, & array k = 0, \\ array \sum_{n = 0}^{N - 1} \cos (\frac{2 π}{N} k (n - d_{L} [n])) = \frac{2 π}{N} k ℜ {j V [k]}, & array k = 1, ⋯, M, \\ array \sum_{n = 0}^{N - 1} \sin (\frac{2 π}{N} k (n - d_{L} [n])) = \frac{2 π}{N} k ℑ {j V [k]}, & array k = 1, ⋯, M, \end{matrix})

where M = ⌊ N /2⌋. The first equation in for k = 0 accounts for a mean value of 1/2 of the duty cycles, which is also the DC value of the unipolar PWM signal p L ( t ).…”

Section: Table‐based Proposed Approachmentioning

confidence: 99%

“…Equations in Chierchie and Paolini are developed for leading‐edge PWM, but they can also be used for trailing edge with two modifications: using

v false[n false] = false(1 - \overset{v}{true} false[n false] false) false/ 2

Section: Table‐based Proposed Approachmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Table‐based PWM for all‐digital RF transmitters

Morales

Chierchie

Mandolesi

et al. 2018

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A high‐resolution all‐digital pulse‐width modulator architecture with a tunable delay element in CMOS

Morales

Chierchie

Mandolesi

et al. 2020

Self Cite

An all-digital high-resolution pulse-width modulator in standard 130-nm CMOS technology is presented in this work. The architecture is based on a digitally-controlled delay element with variable time interval up to 50 ps and adjustable against process, voltage and temperature (PVT) variations. Post-layout simulation results show a linear response between the control word and delay. The PWM modulator uses several delay elements in a hybrid configuration that allows to obtain duty cycles with 18-bit resolution, without using a high-frequency internal clock while maintaining low power consumption.

A high‐resolution hybrid digital pulse width modulator with dual‐edge‐triggered flip‐flops and hardware compensation

Cheng

Zhu

et al. 2020

SummaryIn this paper, a hybrid architecture of digital pulse width modulator (DPWM) which applies a counter, a phase‐shifted circuit, and a carry chain is proposed. Dual‐edge‐triggered flip‐flops are used in the phase‐shifted circuit to generate signals with 45° phase shift, which not only improves the resolution of the DPWM but also reduces the resource consumption in the carry chain. Furthermore, a hardware compensation method is used to solve the duty cycle increment phenomenon that affects the regulation accuracy of converter. An 11‐bit DPWM with the proposed architecture is implemented and tested by Xilinx Artix‐7 FPGA. The experimental results show a high resolution of 32 ps and a good linearity where R2 is 0.99 and verify the effect of duty cycle compensation.