Digital Design Techniques for Dependable High Performance Computing

Azimi, Sarah; Sterpone, Luca

doi:10.1109/itc44778.2020.9325281

Cited by 12 publications

(4 citation statements)

References 21 publications

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“…The probability of faults due to voltage glitches induced by ionizing particles in digital chips increase with the reduction of the minimum feature size and voltage margins, along with augmented statistical process variations [1], [2], [3]. The ability to manage circuit faults to preserve the system's functional safety, commonly denoted as fault tolerance (FT), is traditionally linked to space, avionics, and military worlds.…”

Section: Introductionmentioning

confidence: 99%

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

et al. 2022

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Fault management in digital chips is a crucial aspect of functional safety. Significant work has been done on gate and microarchitecture level triple modular redundancy, and on functional redundancy in multi-core and simultaneous-multi-threading processors, whereas little has been done to quantify the fault tolerance potential of interleaved-multi-threading. In this study, we apply the temporal-spatial triple modular redundancy concept to interleaved-multi-threading processors through a design solution that we call Buffered triple modular redundancy, using the soft-core Klessydra-T03 as the basis for our experiments. We then illustrate the quantitative findings of a large fault-injection simulation campaign on the fault-tolerant core and discuss the vulnerability comparison with previous representative fault-tolerant designs. The results show that the obtained resilience is comparable to a full triple modular redundancy at the cost of execution cycle count overhead instead of hardware overhead, yet with higher achievable clock frequency.INDEX TERMS Circuit faults, digital integrated circuits, fault detection, fault tolerant computing, field programmable gate arrays, microprocessors, multithreading, radiation hardening (electronics), redundancy, robustness.Open Access funding provided by 'Università degli Studi di Roma ''La Sapienza''' within the CRUI CARE Agreement

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Section: Introductionmentioning

confidence: 99%

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

et al. 2022

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“…Radiation can significantly impact the reliability of electronic systems [9]. This is a major issue in space and avionics applications, which can be exposed to high fluxes of high energy particles, and it is also one of the main concerns for the reliability of safety-critical systems working at sea level, where cascades of secondary particles due to solar activity interacting with the upper atmosphere can be the source of radiation-induced disturbance in the devices [10].…”

Section: Background On Radiation Effects In Reconfigurable Hardwarementioning

confidence: 99%

Exploring the Impact of Soft Errors on the Reliability of Real-Time Embedded Operating Systems

et al. 2022

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The continuous scaling of electronic components has led to the development of high-performance microprocessors that are suitable even for safety-critical applications where radiation-induced errors such as Single Event Effects (SEEs) can have a significant impact on the performance and reliability of the system. This work is dedicated to investigating the reliability of systems based on programmable hardware and Real-time operating Systems (RTOS) in the presence of architectural faults induced by soft errors in the configuration memory of the programmable hardware. We performed a proton radiation test campaigned at PSI radiation facility to identify the fault model affecting the configuration memory of Xilinx Zynq-7020 reconfigurable AP-Soc Device. The identified fault model in terms of SEU and MBU clusters has been used to evaluate the impact of proton-induced faults on applications running within FreeRTOS on a Microblaze soft processor. A Single Event Multiple Upset fault model resulting from a proton test is presented, focusing on characteristics such as shape, size, and frequency of observed cluster of errors. We conduct two fault injection campaigns and analyze the results to assess the effect of cluster size on system reliability. Moreover, we discuss software exceptions caused by faults that can affect the hardware structure of the soft processor.

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“…In the last few decades, the growing complexity of electronic systems employed in the automotive, aerospace, military, and generally in safety-critical applications has increased the importance of fault-tolerant design and fault simulation. Moreover, the probability of faults in digital electronic devices has increased with technology scaling, voltage margin reduction, and statistical process variations magnification [1][2][3]. As a consequence, faulttolerance (FT) techniques for functional safety support in microprocessor cores have become a requisite in many system designs.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core

Barbirotta

Cheikh

Mastrandrea

et al. 2022

JLPEA

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Functional safety is a key requirement in several application domains in which microprocessors are an essential part. A number of redundancy techniques have been developed with the common purpose of protecting circuits against single event upset (SEU) faults. In microprocessors, functional redundancy may be achieved through multi-core or simultaneous-multi-threading architectures, with techniques that are broadly classifiable as Double Modular Redundancy (DMR) and Triple Modular Redundancy (TMR), involving the duplication or triplication of architecture units, respectively. RISC-V plays an interesting role in this context for its inherent extendability and the availability of open-source microarchitecture designs. In this work, we present a novel way to exploit the advantages of both DMR and TMR techniques in an Interleaved-Multi-Threading (IMT) microprocessor architecture, leveraging its replicated threads for redundancy, and obtaining a system that can dynamically switch from DMR to TMR in the case of faults. We demonstrated the approach for a specific family of RISC-V cores, modifying the microarchitecture and proving its effectiveness with an extensive RTL fault-injection simulation campaign.

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Digital Design Techniques for Dependable High Performance Computing

Cited by 12 publications

References 21 publications

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Exploring the Impact of Soft Errors on the Reliability of Real-Time Embedded Operating Systems

Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core

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