Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core

Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Ottavi, Marco; Olivieri, Mauro

doi:10.3390/jlpea13010002

Cited by 13 publications

(10 citation statements)

References 40 publications

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“…The framework for this study is the Klessydra-fT13 architecture, a fault-tolerant 32-bit RISC-V IMT soft processor integrated inside the PULPino [23] open-source System-on-Chip architecture. The processor is composed of a fault-tolerant non-accelerated scalar core, resembling Klessydra fT03 [7][8][9], tightly coupled with a fault-tolerant configurable accelerating co-processor unit (Figure 1).…”

Section: Methodsmentioning

confidence: 99%

“…We aim to start from the use of an Interleaved-Multi-Threading (IMT) core modified to achieve fault-tolerant execution [7][8][9] thanks to the implementation of a new FT technique called Buffered Triple-Modular Redundancy (TMR), able to integrate both TMR and temporal redundancy, adding the support of a vector acceleration unit [10,11] and describing all the performance in terms of fault tolerance and reliability to obtain a completely fault-tolerant accelerated core.…”

Section: Introductionmentioning

confidence: 99%

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Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes

Barbirotta,

Cheikh,

Mastrandrea

et al. 2023

Electronics

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High-performance embedded systems with powerful processors, specialized hardware accelerators, and advanced software techniques are all key technologies driving the growth of the IoT. By combining hardware and software techniques, it is possible to increase the overall reliability and safety of these systems by designing embedded architectures that can continue to function correctly in the event of a failure or malfunction. In this work, we fully investigate the integration of a configurable hardware vector acceleration unit in the fault-tolerant RISC-V Klessydra-fT03 soft core, introducing two different redundant vector co-processors coupled with the Interleaved-Multi-Threading paradigm on which the microprocessor is based. We then illustrate the pros and cons of both approaches, comparing their impacts on performance and hardware utilization with their vulnerability, presenting a quantitative large-fault-injection simulation analysis on typical vector computing benchmarks, and comparing and classifying the obtained results. The results demonstrate, under specific conditions, that it is possible to add a hardware co-processor to a fault-tolerant microprocessor, improving performance without degrading safety and reliability.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes

Barbirotta,

Cheikh,

Mastrandrea

et al. 2023

Electronics

Self Cite

View full text Add to dashboard Cite

show abstract

“…Temporal redundancy is in fact, widely used in different embedded platforms, including multi-core and multi-threaded architectures [25]- [28] where the aspect of redundant multithreading at application-level holds notable significance, as highlighted in [29], [30]. Regarding HPC systems, some effort has been done to achieve temporal redundancy via software replication.…”

Section: Related Workmentioning

confidence: 99%

Enhancing Fault Tolerance in High-Performance Computing: A real hardware case study on a RISC-V Vector Processing Unit

Barbirotta,

Minervini,

Morales

et al. 2024

Preprint

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“…Many fault-tolerant techniques were developed over the years based on multi-thread and multi-core architectures [16]. In Multi-Core (MC) architectures, some approaches were adapted from the Simultaneous Multi-Threading (SMT) field [1].…”

Section: Related Workmentioning

confidence: 99%

A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection

Vigli,

Barbirotta,

Cheikh

et al. 2024

IEEE Access

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The low probability of single event upsets (SEU) within particular satellite orbits, makes Commercial-off-the-shelf (COTS) electronic components a viable solution for space system implementation, thanks to the introduction of design-level fault tolerance techniques at the expense of some performance/energy/area penalty. This paper illustrates the design and validation of a novel RISC-V dualcore architecture, based on a computing paradigm that we refer to as full/partial heterogeneous multi-core protection. The approach relies on a small, low-performance, fully fault-tolerant core (LP core) coupled with a high-performance partially fault-tolerant core (HP core). The computing paradigm assumes the failureexposed HP core executes computation intensive routines for relatively short periods of time, making the occurrence of failures a statistically unlikely situation, while the fully fault-tolerant LP core operates in critical control tasks and manages the failure recovery of the high-performance core. The execution time percentage in the LP core varies from a minimum of 11.4% up to a maximum of 91.3% while in the HP core it is between 8.7% and 88.6%, depending on the application. In the proposed study, both the cores belong to the RISC-V compliant Klessydra core family. The dual-core architecture also includes a watchdog timer controlled by the LP core and monitoring the non-protected HP core, and a context switch FIFO that speeds up the code and data switch between the two cores during failure recovery. A dedicated run-time software environment coordinates the execution of tasks on the high-performance core in a resilient fashion. The dual-core processor has been validated through extensive RTL simulations running in an UVM-based faultinjection environment, which emulates SEUs at various rates. Experimental results illustrate the benefits and limits obtained by using a heterogeneous architecture with different levels of protection and performance. The failure probability assuming a SEU fault occurrence can be reduced by a factor between 10X and 30X with respect to the non-protected architecture, leading to an average failure rate of up to 4.00E-06 per second with respect to 1.80E-05 per second in the non-protected architecture.

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Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core

Cited by 13 publications

References 40 publications

Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes

Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes

Enhancing Fault Tolerance in High-Performance Computing: A real hardware case study on a RISC-V Vector Processing Unit

A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection

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