Digital Background Correction of Harmonic Distortion in Pipelined ADCs

On Calibration Techniques for Pipelined ADCs

“…By using redundancy bits, the digital error correction technique has been applied to rectify the comparator offset error. But there are some disadvantages with these two techniques like decrease in amplitude of the transmitting, slow convergence speed and deduction of the redundancy space [24][25][26][27]. To overcome these disadvantages, instead of using the pseudorandom noise dither, the variable-amplitude dithering has been used for a digital calibration algorithm for domain-extended pipelined ADCs [10].…”

Digital nonlinearity calibration for pipelined ADCs using sampling capacitors splitting

“…A variant of the two-mode technique was introduced in [3], where a covariance computation helped avoid input distribution dependency, at the cost of significantly increased digital circuit complexity. In [4], the HDC technique inserts several calibration sequences into the MDAC input, extracts the parameters of f(x) at the output of backend stages, and uses b 1 % 1=a 1 , b 3 % Àa 3 =a 1 3 to approximate the correction function g(x), but this approximation limits the degree of nonlinear errors it can handle, furthermore, the correlation used to extract a 1 and a 3 leads to a very long convergence time. In all the preceding works, a common idea is to first linearize the combined function g(f(x)), by solving b 3 , then the linear gain estimation of b 1 becomes an easy work given many existing methods [3,4,6], therefore, the way to solve b 3 is the main determinant of the technique's performance and efficiency.…”

“…However, as device sizes continuously scale down, the amplifier nonlinearities has become more and more prominent, severely degrading the ADC performance, especially at high conversion rates when the conventional high-gain amplifiers are no longer proper due to limited settling speed. Several nonlinearity calibration techniques have been published [1,2,3,4] but few has been widely accepted as a practical solution, due to either the very limited nonlinearity correcting ranges or the effective correction relying on certain input distributions. This paper proposes a novel digital background calibration scheme to correct severe nonlinearity errors of inter-stage residue amplifiers in pipelined ADCs.…”

Nonlinear inter-stage gain calibration for pipelined ADCs employing double dithering modes

“…(1) gives D in ¼ cV in , ensuring the ADC a linear quantization curve. On the other hand, when the inter-stage amplifier is nonlinear (for example, when the closed-loop gain is not adequate), fully-differential circuit implementations commonly present fðxÞ as an odd polynomial (offset is assumed to be canceled by other techniques such as that in [5]), in this case, another odd polynomial is needed for gðxÞ to linearize the combined function gðfðxÞÞ so that linear gain calibration can be successfully performed, in most cases, a 3 rd order polynomial is qualified for gðxÞ [1,2,3], as shown in Fig. 1.…”

“…However, few of related works ever published well covers all of the concerns mentioned above. For example, the calibration scheme proposed in [1] is activated only at certain input levels, which severely limits its adaptability to any input signal distributions, furthermore, only weak nonlinear error is correctable; the technique in [2] is highly effective regardless of input distributions, but it takes very long time for calibration parameters to converge; the technique in [3] utilizes the proportionality feature of linear systems for error estimation, and presents both input signal independency and fast convergence, but the randomly attenuation applied to input magnitude significantly deteriorates SNR, and the linear and nonlinear error calibration processes have to be performed separately.…”