A new technique for the fabrication of planar junctions in gallium arsenide, by diffusion from tin-doped silicon dioxide layers, has been investigated. It has been found that the doped oxide should contain less than 10% by weight of tin to prevent the occurrence of molten phases at the diffusion temperature (...I010~ Under these conditions, the junction depth increases as the square root of diffusion time for thick oxides and short diffusion times. However, the junction depth can also decrease with increasing diffusion time due to dopant depletion in the oxide if the oxide is thin and the diffusion time is large. Planar diffusions from tin-doped oxides have been performed in evacuated quartz ampuls, with no arsenic overpressure, using phosphosilicate glass films as diffusion masks. Lateral diffusions of less than twice the junction depth have been achieved by using masks with 15% by weight of P205. These diffusions have been performed under conditions that appear to be more severe than those expected during open-tube diffusion. Thus, the results indicate that the doped oxide diffusion technique should be suitable for the development of an open-tube planar diffusion process for the fabrication of gallium arsenide devices and integrated circuits. Semiconductor Grade, Matheson Gas Products, East Rutherford, Massachusetts. 135 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 169.230.243.252 Downloaded on 2015-03-23 to IP
ABSTRACTThe influence of meltback on dopant distribution in silicon liquid phase epitaxial layers has been examined for heavily boron-doped substrates. Meltback has been shown to produce a graded p-type layer at the interface between the layer and the substrate. An analysis is presented to demonstrate that this layer has an exponentially graded profile and several experiments are described which demonstrate that the boron is uniformly distributed in the melt during epitaxial growth. In addition, growth conditions are described to prevent the formation of this p-type layer and to achieve an abrupt interface between the epitaxial layer and the substrate.In previous papers it has been demonstrated that epitaxial layers of silicon can be grown by liquid phase 9 ~-lectrochemical Society Active Member. epitaxy by using tin as a solvent for silicon (1-3). In these papers, the kinetics of the epitaxial growth process and the morphology of the resulting layers were ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 169.230.243.252 Downloaded on 2015-03-23 to IP