Diffusion of group III and V elements in SiO2

Ommen, A. H. van

doi:10.1016/0169-4332(87)90100-0

Cited by 26 publications

(10 citation statements)

References 31 publications

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“…On the contrary, a large number of Ga vacancies form at the SiO 2 /GaAs interface during RTA with the SiO 2 cap, which is due to a fast Ga outdiffusion into the SiO 2 layer during thermal annealing. 19 Ga vacancies diffuse into the QDs region during RTA, enhancing the In/Ga interdiffusion through a dot/cap interface. 12,13 That process affects mainly the QD height, which results in a blueshift and narrowing of the optical emission with no destruction of the threedimensional carrier confinement in the QDs.…”

Section: Aplmentioning

confidence: 99%

Rapid thermal annealing of InAs/GaAs quantum dots under a GaAs proximity cap

Babiński

Jasiński

Bożek

et al. 2001

Applied Physics Letters

108

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The effect of postgrowth rapid thermal annealing (RTA) on GaAs proximity-capped structures with self-assembled InAs/GaAs quantum dots (QDs) is investigated using transmission electron microscopy (TEM) and photoluminescence (PL). As can be seen from the TEM images, QDs increase their lateral sizes with increasing annealing temperature (up to 700 °C). QDs cannot be distinguished after RTA at temperature 800 °C or higher, and substantial thickening of the wetting layer can be seen instead. The main PL peak blueshifts as a result of RTA. We propose that in the as-grown sample as well, as in samples annealed at temperatures up to 700 °C, the peak is due to the QDs. After RTA at 800 °C and higher the PL peak is due to a modified wetting layer. Relatively fast dissolution of QDs is explained in terms of strain-induced lateral Ga/In interdiffusion. It is proposed that such a process may be of importance in proximity-capped RTA, when no group-III vacancy formation takes place at the sample/capping interface.

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Section: Aplmentioning

confidence: 99%

Rapid thermal annealing of InAs/GaAs quantum dots under a GaAs proximity cap

Babiński

Jasiński

Bożek

et al. 2001

Applied Physics Letters

108

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“…It has been demonstrated that a large number of Ga vacancies is formed at the SiO 2 / GaAs interface during RTA with a SiO 2 capping layer, which is due to a fast Ga outdiffusion into the SiO 2 layer during thermal annealing. 29 Ga vacancies diffuse into the QD region during RTA ͑Ref. 30͒ and enhance the As diffusion that resulted from the QD dissolution.…”

Section: Resultsmentioning

confidence: 99%

Effect of rapid thermal annealing on the noise properties of InAs∕GaAs quantum dot structures

Arpatzanis

Tsormpatzoglou

Dimitriadis

et al. 2007

Journal of Applied Physics

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Combined optical and electrical studies of the effects of annealing on the intrinsic states and deep levels in a self-assembled InAs quantum-dot structure Self-assembled InAs quantum dots ͑QDs͒ were grown by molecular beam epitaxy ͑MBE͒ on n + -GaAs substrates, capped between 0.4 m thick n-type GaAs layers with electron concentration of 1 ϫ 10 16 cm −3 . The effect of rapid thermal annealing at 700°C for 60 s on the noise properties of the structure has been investigated using Au/ n-GaAs Schottky diodes as test devices. In the reference sample without containing QDs, the noise spectra show a generation-recombination ͑g-r͒ noise behavior due to a discrete energy level located about 0.51 eV below the conduction band edge. This trap is ascribed to the M4 ͑or EL3͒ trap in GaAs MBE layers, related to a chemical impurity-native defect complex. In the structure with embedded QDs, the observed g-r noise spectra are due to a midgap trap level ascribed to the EL2 trap in GaAs, which is related to the InAs QDs dissolution due to the thermal treatment.

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“…Similar to Ge, indium diffusion in SiO 2 has been proposed to occur via slow In + ion diffusion and fast oxygenenhanced diffusion mechanisms. 6 Oxygen-enhanced In diffusivities have been found to be on the order of 1e-13 cm 2 /s in thermal oxide at temperatures relevant to this work. 27,28 For the InP-OI SOLES wafers demonstrated here, since a majority of the BOX layer is comprised of PECVD SiO 2 , a fast diffusion mechanism such as oxygen-enhanced diffusion is very likely.…”

Section: P264mentioning

confidence: 94%

“…With reference to the former, the P 2 O 5 structure is relatively immobile in SiO 2 . 6 With reference to the latter, SiO 2 -P 2 O 5 has a eutectic …”

mentioning

confidence: 99%

Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates

Pacella

Bulsara

Drazek

et al. 2015

ECS J. Solid State Sci. Technol.

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The Silicon on Lattice Engineered Substrate (SOLES) platform enables monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal oxide semiconductor (CMOS) devices. The SOLES wafer provides a device quality Si-on-Insulator (SOI) layer for CMOS device fabrication and an embedded III-V device template layer which serves as a seed surface for epitaxial growth of III-V devices. In this work, different approaches for fabricating SOLES wafers comprised of Ge and InP template layers are characterized and InP-based SOLES structures are demonstrated for the first time. Ge-based SOLES are robust for long durations at temperatures up to 915 • C and Ge diffusion can be controlled by engineering the oxide isolation layers adjacent to the Ge. InP SOLES structures alleviate lattice and thermal expansion mismatches between the template layer and subsequent device layers. Although allowable processing temperatures for these wafers had been expected to be higher due to the higher melting temperature of InP, high indium diffusion through the SiO 2 and InP melting actually lead to lower thermal stability. This research elucidates approaches to enhance the process flexibility and wafer integrity of Ge-based and InP-based SOLES. Monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal-oxide semiconductor (CMOS) enables advanced circuits with increased performance and functionality and promotes system-level miniaturization. The Silicon on Lattice Engineered Substrate (SOLES) platform is a Si wafer with embedded III-V template layer that has been developed for III-V/Si integration and is illustrated in Fig. 1. 1,2 A silicon-on-insulator (SOI) layer on top provides the high quality substrate necessary for CMOS device processing whereas the III-V template acts as a seed layer for epitaxial III-V device growth. This III-V template layer is accessed by etching windows through the top Si and buried insulator layers. The SOLES substrate structure is designed to add functionality to a CMOS platform while maintaining compatibility with Si processing infrastructure. Exposure to the III-V template layer is avoided until the CMOS process sequence is complete and the III-V device epitaxy and processing can be treated in a similar manner to backend metal processing.

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Diffusion of group III and V elements in SiO2

Cited by 26 publications

References 31 publications

Rapid thermal annealing of InAs/GaAs quantum dots under a GaAs proximity cap

Rapid thermal annealing of InAs/GaAs quantum dots under a GaAs proximity cap

Effect of rapid thermal annealing on the noise properties of InAs∕GaAs quantum dot structures

Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates

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