Dielectric Breakdown and Current Conduction of Oxide/Nitride/Oxide Multi‐Layer Structures

Abstract

We present a detailed study on the effect of bottom-and top-oxide thicknesses on the current conduction and the dielectric breakdown of oxide/nitride/oxide (ONO) multi-layer dielectrics. An abrupt reduction in current is observed when the oxide that is contiguous to the anode is thicker than 3 nm. This leads us to conclude that the thick oxide (>3 nm) impedes hole injection from anode into nitride. The injected charge-to-breakdown (QBD) and the time-to-breakdown (TBD) are measured to study the breakdown mechanism. We observe that a substantial increase in TBD occurs in spite of the reduction in QBD when the thick oxide is contiguous to anode. This phenomenon is explained by a hole-induced breakdown model for the ONO structure with thin bottom-and top-oxides (<3 nm). Hole injection is suppressed by the thick oxide that is contiguous to anode. The increase in TBD is attributed to the reduction in injected holes. We conclude that the dielectric breakdown of the ONO structure with the thin oxides is induced by injected holes. We also observe that the thermal activation energy of the TSD changes at 3 nm in bottom-oxide thickness under negative gate bias. Therefore, this value of 3 nm is determined as a threshold thickness for the change of the breakdown mechanism.

High performance sub-0.25 /spl mu/m devices using ultrathin oxide-nitride-oxide gate dielectric formed with low pressure oxidation and chemical vapor deposition

“…The ONO gate stack was formed in four major process steps: after a conventional pre-gate oxide clean, the silicon surface was first oxidized in oxygen at a pressure of 800 mtorr and a temperature of 750 C to form an oxide thickness of 10 Å. Twenty Å of silicon nitride was then deposited on the oxidized layer at a pressure of 100 mtorr and a temperature of 800 C using dichlorosilane and ammonia as deposition precursors. To establish an electrical contact with poly-si electrode [9] and suppress gate leakage current [17], the dual layer was then topped with a 10 Å Tetraethoxysilane (TEOS) oxide deposited at a pressure of 450 mtorr and a temperature of 700 C. The TEOS oxide is needed to suppress gate leakage current. The whole ONO stack was then in-situ densified in N O gases at the TEOS deposition temperature and then ex-situ annealed with a rapid thermal process (900 C for 30 s in nitrogen) which reduces SiO /Si interfacial defect density and fixed charge density [11].…”

“…3(b). The nitrogen at the interface is one of the reasons that the dielectric reliability is improved [17]. However, the amount of nitrogen is not high enough to reduce carrier mobility.…”

Characterization of ultra thin high K gate dielectrics by grazing x-ray reflectance and Spectroscopic Ellipsometry on the same instrument

“…Nitride/oxide gate dielectrics have already been widely used [2][3]. Materials other than silicon nitride, while attractive from the dielectric constant viewpoint show additional problem.…”

Constant current-stress-induced breakdown of reoxidized nitrided oxide (ONO) in flash memory devices

“…The feasibility of ionic conduction within the ONO layer is also of prime importance to the charge retention capability in the non-volatile memory devices. Several authors [1]-[3J have studied this ionic conduction in silicon nitride and ONO structures, and discussed their breakdown phenomena. K. Kobayashi etaL [1] presented a detailed discussion on the effect of the bottom-and top-oxide thickness on the current conduction and the dielectric breakdown.…”

“…The constant current-stressing technique is a simple straight forward method to assess the integrity of the dielectric layer. For Flash devices, various authors [1,4,5] have shown that both electrons and holes can be easily injected from the polysilicon layers into the ONO dielectric layer, which is sandwiched between them. We strongly believe that any variations in the material properties of the polysilicon electrodes, especially those changes which can cause reductions in the carriers' flow through the polysilicon and oxides, or improve the conditions of the interfaces between the polysilicon layers and oxides, can constitute a substantial increase in the dielectric layer breakdown time [6].…”