Die size reduction by optimizing the dimensions of the vertical feedthrough pitch and sealing area in the advanced MEMS (aMEMS) process

Torunbalcı, Mustafa Mert; Alper, Said Emre; Akın, Tayfun

doi:10.1109/isiss.2015.7102380

Cited by 5 publications

(4 citation statements)

References 11 publications

(22 reference statements)

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“…The current pitch size of the fabricated vertical feedthroughs and via openings is selected to be 700 μm, in order to stay on the safe side during the initial demonstration of the concept. This pitch size can be easily reduced down to 350 μm by reducing the thickness of the handle layer of the SOI cap wafer [23], [24]. Further reduction is also possible as described in [24].…”

Section: B Fabricationmentioning

confidence: 99%

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Advanced MEMS Process for Wafer Level Hermetic Encapsulation of MEMS Devices Using SOI Cap Wafers With Vertical Feedthroughs

Torunbalcı

Alper

Akın

2015

J. Microelectromech. Syst.

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This paper reports a novel and inherently simple fabrication process, so-called advanced MEMS (aMEMS) process, that is developed for high-yield and reliable manufacturing of wafer-level hermetic encapsulated MEMS devices. The process enables lead transfer using vertical feedthroughs formed on an Silicon-On-Insulator (SOI) wafer without requiring any complex via-refill or trench-refill processes. It requires only seven masks to fabricate the hermetically capped sensors with an experimentally verified process yield of above 80%. Hermetic encapsulation is achieved by Au-Si eutectic bonding at 400°C, and the pressure inside the encapsulated cavity has been characterized to be as low as 1 mTorr with successfully activated thin-film getters. The pressure inside the encapsulated cavity can also be adjusted in the range of 1 mTorr-5 Torr by various combinations of outgassing and gettering options in order to satisfy the requirements of different applications. The package pressure is being monitored for the selected chips and is observed to be stable below 10 mTorr since their fabrication about 10 months ago. The shear strengths of several packages are measured to be as high as 30 MPa with average shear strength of 22 MPa, indicating a mechanically strong bonding. The robustness of the packages is tested by thermal cycling between 100°C and 25°C, and absolutely no degradation is observed in the hermeticity and the package pressure. The package pressure is also verified to remain unchanged after storing the packages at a high storage temperature of 150°C for 24 h. Furthermore, the packaged chips are observed to withstand a high temperature shock test performed at 300°C for 5 min, at the end of which the characteristics of the encapsulated sensor indicates that the package still remains hermetic (no detectable leaks) and also the package pressure remains constant at ∼20 mTorr.[ 2014-0338]Index Terms-Microelectromechanical systems (MEMS), wafer level hermetic encapsulation, Au-Si eutectic bonding, vertical feedthroughs, advanced MEMS process (aMEMS).

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Section: B Fabricationmentioning

confidence: 99%

“…This pitch size can be easily reduced down to 350 μm by reducing the thickness of the handle layer of the SOI cap wafer [23], [24]. Further reduction is also possible as described in [24].…”

Section: B Fabricationmentioning

confidence: 99%

Advanced MEMS Process for Wafer Level Hermetic Encapsulation of MEMS Devices Using SOI Cap Wafers With Vertical Feedthroughs

Torunbalcı

Alper

Akın

2015

J. Microelectromech. Syst.

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“…The thickness of the handle layer determines the TSV dimensions and it is selected as 300 μm in this study. However, it can be reduced to sub-100 μm by reducing the thickness of the handle layer and using a smaller wire bonder capillary [40]. The TSVs are directly bonded on the device electrodes, eliminating the need for any device metallization and thereby reducing the undesired parasitics.…”

Section: Advanced Mems Processmentioning

confidence: 99%

An All-Silicon Process Platform for Wafer-Level Vacuum Packaged MEMS Devices

Torunbalcı

Gavcar²,

Yesil³

et al. 2021

IEEE Sensors J.

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This paper introduces a novel, inherently simple, and all-silicon wafer-level fabrication and hermetic packaging method developed for MEMS devices. The proposed method uses two separate SOI wafers to form highly-doped through-silicon vias (TSVs) and suspended MEMS structures, respectively. These SOI wafers are then bonded by Au-Si eutectic bonding at 400 • C, achieving hermetic sealing and signal transfer without requiring any complex via or trench refill process steps. The package vacuum is measured using encapsulated MEMS resonators to be as low as 15 mTorr with the help of successfully activated thin-film getters. The combined fabrication and packaging yield is around %89 and chips still maintain a package pressure below 100 mTorr after more than 6 years. The packages show an extremely high strong bonding strength (>40 MPa) and are proved to remain hermetic after temperature cycling (25 • C-85 • C) and harsh temperature shock (5 min@300 • C) tests. The all-silicon MEMS resonators fabricated and packaged using the proposed method project up to a 2.3× enhancement in the bias instability and ∼4× in the temperature sensitivity of frequency output compared to an identical MEMS resonator fabricated using the silicon-on-glass (SOG) technology.Index Terms-Wafer level vacuum packaging, through silicon via (TSV), MEMS devices. I. INTRODUCTIONT HE operating environment is a key factor in determining the functional behavior of Micro-Electro-Mechanical Systems (MEMS) devices. Some of the MEMS devices including but not limited to gyroscopes, oscillators, and microbolometers require a vacuum-sealed environment for achieving high-performance operation. This unique requirement makes the hermetic encapsulation a crucial step for the commercialization of MEMS devices [1]- [3].There are two common approaches for wafer-level hermetic encapsulation of MEMS devices. The first approach uses the conventional thin film deposition techniques in order to form a capping layer on top of a suspended MEMS structure [4]- [10].

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“…Figures 3 and 4 show optical and SEM photographs of the fabricated MEMS chips and encapsulated sensors, respectively. The via pitch is selected as 600 μm for the initial proof of concept trials, which can be easily reduced to 350 μm by thinning the handle layer of the SOI wafer as in [16,19]. The die size is 5 mm × 4.5 mm for this particular case, but this may also be further decreased by reducing the vertical feedthrough pitch.…”

Section: Process Design and Fabricationmentioning

confidence: 99%

A method for wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process

Torunbalcı¹,

Alper²,

Akın³

2015

J. Micromech. Microeng.

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This paper presents a novel, inherently simple, and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where a single SOI wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a single glass cap wafer is used for hermetic encapsulation and routing metallization. Hermetic encapsulation can be achieved either with the silicon-glass anodic or Au–Si eutectic bonding techniques. The dies sealed with anodic and Au–Si eutectic bonding provide a low vertical feedthrough resistance around 50 Ω. Glass-to-silicon anodically and Au–Si eutectic bonded seals yield a very stable cavity pressure below 10 mTorr with thin-film getters, which are measured to be stable even after 311 d. The package pressure can be adjusted from 5 mTorr to 20 Torr by using different outgassing, cavity depth, and gettering options. The packaging yield is observed to be around 64% and 84% for the anodic and Au–Si eutectic packages, respectively. The average shear strength of the anodic and eutectic packages is measured to be higher than 17 MPa and 42 MPa, respectively. Temperature cycling, high temperature storage, and ultra-high temperature shock tests result in no degradation in the hermeticity of the packaged chips, proving perfect thermal reliability.

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Die size reduction by optimizing the dimensions of the vertical feedthrough pitch and sealing area in the advanced MEMS (aMEMS) process

Cited by 5 publications

References 11 publications

Advanced MEMS Process for Wafer Level Hermetic Encapsulation of MEMS Devices Using SOI Cap Wafers With Vertical Feedthroughs

Advanced MEMS Process for Wafer Level Hermetic Encapsulation of MEMS Devices Using SOI Cap Wafers With Vertical Feedthroughs

An All-Silicon Process Platform for Wafer-Level Vacuum Packaged MEMS Devices

A method for wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process

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