Diagnosis Framework for Locating Failed Segments of Path Delay Faults

Chen, Ying-Yen; Liou, Jing-Jia

doi:10.1109/tvlsi.2008.2000367

Cited by 28 publications

(34 citation statements)

References 25 publications

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“…People have been using at-speed scan test patterns to identify delay defects during product silicon debug [11][12][13][14][15][16][17][18][19][20][21][22]. Path delay fault model has been used in previous works to diagnose delay defects [12] [13] [14] [15], but the diagnostic resolution for path delay faults hasn't achieved an acceptable level, especially when there are multiple faults in the circuit under diagnosis.…”

Section: Review Of Previous Workmentioning

confidence: 99%

“…Path delay fault model has been used in previous works to diagnose delay defects [12] [13] [14] [15], but the diagnostic resolution for path delay faults hasn't achieved an acceptable level, especially when there are multiple faults in the circuit under diagnosis. To improve the diagnosis resolution of path delay faults, people have proposed to use additional test patterns [16] [17] to target sensitized paths. The additional patterns can be used to find the delay bound of suspect paths to help improve diagnostic resolution.…”

Section: Review Of Previous Workmentioning

confidence: 99%

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Speed-Path Debug Using At-Speed Scan Test Patterns

Guo

Cheng

Tsai

2009

2009 14th IEEE European Test Symposium

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Speed path debug is a critical step to improve the performance of high performance VLSI designs. The purpose of speed path debug is to identify the performance limiting paths and fix them in the next product stepping so that the chip can run at a higher clock frequency. This paper investigates speed path debug techniques using atspeed scan test patterns. For each failing scan cell, the failing paths are identified based on structural analysis of logic simulation values. We further propose two metrics to rank the identified speed paths based on logic value analysis and based on timing information calculated for the failing pattern. Experimental results show the effectiveness of the proposed speed path debug technique.

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Section: Review Of Previous Workmentioning

confidence: 99%

Section: Review Of Previous Workmentioning

confidence: 99%

Speed-Path Debug Using At-Speed Scan Test Patterns

Guo

Cheng

Tsai

2009

2009 14th IEEE European Test Symposium

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“…The approach in [8] and [9] addresses the problem of isolating defective segments using path delay measurements. In particular, [8] relies on Linear Programming (LP) formulation where inequalities are formed for the segments as well as the paths.…”

Section: Introductionmentioning

confidence: 99%

“…In particular, [8] relies on Linear Programming (LP) formulation where inequalities are formed for the segments as well as the paths. Different instances of LP formulation, each using a different failing path as the objective function, is solved and a ranking of the potential defective segments is derived.…”

Section: Introductionmentioning

confidence: 99%

Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements

Somashekar

Tragoudas

2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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An approach capable of identifying the locations of distributed small delay defects, arising due to manufacturing aberrations, is proposed. It is shown that the proposed formulation can be transformed into a Boolean Satisfiability form to be solved by any SAT solver. The approach is capable of providing a small number of alternative sets of potential defective segments, and one of the solutions is the actual defect configuration. This is shown to be a very important property towards the effective identification of the defective segments. Experimental analysis on ISCAS and ITC benchmark suites show that the proposed approach is highly scalable and identifies the location of multiple delay defects.

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“…This is an important problem because a test vector may sensitize several PDFs that lead to the fault output(s). Using the set of measured suspect paths and/or the TF model, techniques as in [4] [5] [6] [7] [8] [11] among many others, address the problem of pruning the set of suspect defective locations. Some of them are designed for fault-diagnosis and others for post-silicon debug [1].…”

Section: Introductionmentioning

confidence: 99%

Identification of delay defects on embedded paths using one current sensor

Aljubouri

Tragoudas

Haniotakis

2016

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

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This paper is focused on developing an ATPG-based method that is orthogonal to existing post-silicon debug methods for delay defects. Given an embedded path that contains a small number of gates, the proposed ATPG generates two test vectors so that a current sensor can measure its delay with high accuracy. Unless the cumulative defect along the path is very small, the proposed method will either determine that all locations on it are fault-free or some are defective. This will benefit postsilicon debug methods and, ultimately, failure analysis. No modifications are required in the circuit layout and the routing of the power lines. Experimental results on some of the largest ISCAS85, ISCAS89 and ITC99 benchmarks show that the proposed ATPG tool is capable of generating test vectors which measure the delay of embedded paths that cover on average approximately one fourth of the gates. These results indicate the promise of the method.

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Diagnosis Framework for Locating Failed Segments of Path Delay Faults

Cited by 28 publications

References 25 publications

Speed-Path Debug Using At-Speed Scan Test Patterns

Speed-Path Debug Using At-Speed Scan Test Patterns

Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements

Identification of delay defects on embedded paths using one current sensor

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