Diagnosis for wiring interconnects

Cheng, Wu-Tung; Lewandowski, J.; Wu, Ephrem

doi:10.1109/test.1990.114069

Cited by 65 publications

(17 citation statements)

References 19 publications

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“…The problem of testing interconnects against short faults has been extensively studied and test sequences of minimum length for 100 percent detection and diagnosis have been reported [19], [20], [21]. The majority of the works that aim at detecting faults in the wires connecting two adjacent routers has proposed the insertion of BIST blocks in the routers [12], [22], as shown in Fig.…”

Section: A Bist-based Approachmentioning

confidence: 99%

A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip

Cota

Kastensmidt

Cassel

et al. 2008

IEEE Trans. Comput.

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Section: A Bist-based Approachmentioning

confidence: 99%

A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip

Cota

Kastensmidt

Cassel

et al. 2008

IEEE Trans. Comput.

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“…Assuming the multiple stuck-at and bridge fault model, Cheng et al [3] considered the problem of generating minimum-sized test tests for wiring faults in a printed circuit board.…”

Section: Previous Workmentioning

confidence: 99%

Improving the diagnosability of digital circuits

Ravikumar

Sharma²,

Patney³

1999

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)

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Testing and fault-diagnosis of core-based systems are both difficult problems. Being able to identify which module in the core-based system is faulty has become very important. In this paper, we present algorithms to introduce test points for improving the diagnosability of a digital system. We define a measure of diagnosability known as module resolution which relates to the number of circuit modules that are suspected to be faulty after the diagnostic test procedure has been completed. We present a technique to partition the system into subsystems such that they can be tested in isolation. We also concurrently arrive at a test schedule which minimizes the overall effort in diagnostic testing. We have developed a tool called DEBIT for identifying the number, type, and location of test points in the circuit. We report the results of applying the tool on several benchmark circuits.

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“…The first condition is related to the assumption of a non-fixed pattern bchaviour (wired-and, wired-or) for short faults, and the sccond condition tries to maximize the probability of tfctccting a short fault to non-full-BST Paper 8.2 interconnects. This algorithm proceeds by generating a sequence of codes similar to those generated by the selfdiagnosis algorithm [15], but the Hamming distance between sucessive codes is a modified version of the one in [21].…”

Section: Test Program Generationmentioning

confidence: 99%

A boundary scan test controller for hierarchical BIST

Matos

Pinto

Ferreira

1992

Proceedings International Test Conference 1992

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A test controller for BIST of Boundary Scan Boards is described. It consists of a test processor core, with an optimized architecture for controlling the board-level BST infrastructure, and a system level testability bus interjace, allowing the implementation of a hierarchical test strategy. Automatic test pattern generation for this dedicated processor simplifies the task of providing a board-level BIST solution.

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Diagnosis for wiring interconnects

Cited by 65 publications

References 19 publications

A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip

A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip

Improving the diagnosability of digital circuits

A boundary scan test controller for hierarchical BIST

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