A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip

Cota, Érika; Kastensmidt, Fernanda Lima; Cassel, M.; Herve, Marcos; Meirelles, Paulo; Amory, Alexandre M.; Lubaszewski, Marcelo

doi:10.1109/tc.2008.62

Cited by 72 publications

(26 citation statements)

References 26 publications

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“…Lubaszewski et al [22] proposed a post burn-in testing for NoC interconnects, which is based on the at-speed functional testing of several 2 Â 2 meshes in an N Â N NoC. Their method is also capable of detecting faults between distinct interswitch channels.…”

Section: Link Testingmentioning

confidence: 99%

“…The tradeoff seems to be not in favor of pushing further the functional testing approach. From the point of view of a functional test, about 10 percent of the remaining logic faults are undetectable because they are related to unreachable control states [22].…”

Section: Fault Coveragementioning

confidence: 99%

“…Recently, Lubaszewski et al [22], [23] proposed a new post burn-in testing for NoCs, which is based on the atspeed functional testing of several 2 Â 2 meshes in an N Â N NoC. They test each 2 Â 2 mesh using a set of test sequences and patterns.…”

Section: Introductionmentioning

confidence: 99%

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At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs

Kakoee

Bertacco

Benini

2014

IEEE Trans. Comput.

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Abstract-In this work, we propose a distributed functional test mechanism for NoCs which scales to large-scale networks with general topologies and routing algorithms. Each router and its links are tested using neighbors in different phases. The router under test is in test mode while all other parts of the NoC are operational. We use triple module redundancy (TMR) for the robustness of all testing components that are added into the switch. Experimental results show that our functional test approach can detect stuck-at, short and delay faults in the routers and links. Our approach achieves 100 percent stuck-at fault coverage for the data path and 85 percent for the control paths including routing logic, FIFO's control path, and the arbiter of a 5 Â 5 router. We also show that our approach is able to detect delay faults in critical control and data paths. Synthesis results show that the area overhead of our test components with TMR support is 20 percent for covering stuck-at, delay, and short-wire faults and 7 percent for covering only stuck-at and delay faults in the 5 Â 5 router. Simulation results show that our online testing approach has an average latency overhead of 3 percent in PARSEC traffic benchmarks on an 8 Â 8 NoC.

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Section: Link Testingmentioning

confidence: 99%

Section: Fault Coveragementioning

confidence: 99%

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At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs

Kakoee

Bertacco

Benini

2014

IEEE Trans. Comput.

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“…There have been some growing concerns on the testability aspect of on-chip communication architecture [5]- [7]. Other than the challenges on testing the interconnect architecture, the ability to test IPs is also critical during platform validation and high volume manufacturing [8], [9].…”

Section: Introductionmentioning

confidence: 99%

“…Petersen and Oberg [6] proposed a simple scheme for switch and link testing based on a built-in self-test (BIST) design. A channel testing for bridging faults was proposed in [7]. Some DFT techniques integrate test architectures into the SoC to ease testing procedure [5].…”

Section: Introductionmentioning

confidence: 99%

Multi-TAP architecture for IP core testing and debugging on network-on-chip

Rajagopal

Ooi

Marsono

2011

TENCON 2011 - 2011 IEEE Region 10 Conference

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With the trend to deep-sub-micron (DSM) technology, the ability for post-fabrication testing has become a big concern for system-on-chip (SoC) designers. The testing problem of network-based SoCs is categorized into two major parts, intellectual property (IP) core testing and communication infrastructure testing. This paper presents an IP testing platform using multiple-test-access-port (multi-TAP) for mesh-based networkon-chip (NoC). In our approach, the TAP ports of IPs are connected together in a daisy chain. In addition, IEEE 1149.1 standard (JTAG) is used to connect TAPs of IPs to the external tester. The proposed platform provides comprehensive testing and debugging for each individual IP without incurring dependency to other IPs. The main advantage of the proposed platform is the ability to bypass the IPs which are not involved in the process of testing. Hence, It reduces the required number of clock cycles to send test vectors to the IP/IPs under test.

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