At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs

Kakoee, Mohammad Reza; Bertacco, Valeria; Benini, Luca

doi:10.1109/tc.2013.202

Cited by 62 publications

(12 citation statements)

References 45 publications

(50 reference statements)

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“…However, beside [40], this work does not degrade the performance of the applied NoC. Kakoee et al [25] and Tran et al [26] have a significant impact on the performance which are > 10× and > 1.4× the average latency of synthetic benchmarks and execution time of PARSEC, respectively. Although Liu et al [27] and Wang et al [28] presented promising results under PARSEC benchmarks because of the low utilization rates, they still increase the average latency by up to 2.5× and 2× under synthetic benchmarks.…”

Section: Comparison Of Network-on-chip Testingmentioning

confidence: 91%

“…Apparently, the method requires interrupting the connection in order to start the test. Some other methods to test TSVs in a Network-on-Chip use existing techniques of wire testing [25]- [28]. With smart scheduling of these methods, we can even obtain uninterrupted testing that allows the system to maintain its operation during test.…”

Section: Related Workmentioning

confidence: 99%

“…Most works require partial or total preemption in order to test. Works for online NoC-testing in [25]- [28] perform with lower-bound of test periods around 16,000 to 50,000 while still degrading the system performance.…”

Section: Introductionmentioning

confidence: 99%

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A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

et al. 2020

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As one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs), Through-Silicon-Via (TSV) acts as the inter-layer link inside 3D Networks-on-Chip. However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To ensure the correctness of TSV connections at run-time, detecting multiple (clustering) defects is an important feature. While Error Correction Codes are limited by a certain number of detectable faults, using Built-In-Self-Test (BIST) prevents the system from operating normally during the test time. This paper first presents a Parity Product Code (PPC) with the ability to correct one fault and detect, at least, two faults. Second, we present extended PPC (EPPC) to detect multiple defects within the links of Networks-on-Chip by using two or more additional matrices. Furthermore, we present the distance-aware version of EPPC to detect multiple defects by using only one extra matrix. The results show that the distance-aware EPPC can detect 100% of clustering defects and multiple random defects within two and three cycles, respectively. The performance evaluation for Networkon-Chip testing also shows no degradation while providing an extremely short response time (2-3 cycles). INDEX TERMS 3D-ICs, fault-tolerance, error correction code, through-silicon-via, product code, parity check, networks-on-chip, fault-detection.

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Section: Comparison Of Network-on-chip Testingmentioning

confidence: 91%

Section: Related Workmentioning

confidence: 99%

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A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

et al. 2020

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“…Similar to scouting packets, a common method used for fault detection is the broadcasting of test vectors, either during boot-up [Strano et al 2011;Hosseinabady et al 2007] or at runtime. In order to mitigate the performance degradation caused by testing interruptions, token-based mechanisms have been explored [Kakoee et al 2011a[Kakoee et al , 2014 as well as hardware for monitoring specific modules, such as the router arbiters or datapath components [Seitanidis et al 2014]. A well-established technique to the problem of compromised/corrupted transmission of packets between routers is the use of Error Detecting/Correcting Codes (EDC/ECC).…”

Section: Detection/localizationmentioning

confidence: 99%

An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures

Chrysanthou

Englezakis

Prodromou

et al. 2016

ACM Trans. Archit. Code Optim.

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Networks-on-Chip (NoC) are becoming increasingly susceptible to emerging reliability threats. The need to detect and localize the occurrence of faults at runtime is steadily becoming imperative. In this work, we propose NoCAlert, a comprehensive online and real-time fault detection and localization mechanism that demonstrates 0% false negatives within the interconnect for the fault models and stimulus set used in this study. Based on the concept of invariance checking, NoCAlert employs a group of lightweight microchecker modules that collectively implement real-time hardware assertions. The checkers operate concurrently with normal NoC operation, thus eliminating the need for periodic, or triggered-based, self-testing. Based on the pattern/signature of asserted checkers, NoCAlert can pinpoint the location of the fault at various granularity levels. Most important, 97% of the transient and 90% of the permanent faults are detected instantaneously, within a single clock cycle upon fault manifestation. The fault localization accuracy ranges from 90% to 100%, depending on the desired localization granularity. Extensive cycle-accurate simulations in a 64-node CMP and analysis at the RTL netlist-level demonstrate the efficacy of the proposed technique.

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“…If there is any local fault on the network, it may be in router or link or Processing Element (PE) or in Network Interface (NI) element. Due to this fault [2], [3], there may be a chance for the packet to enter into the deadlock or live lock or packet loss. Then packet has to remap once again which leads to performance degradation.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of secured agent based NoC using shortest path routing algorithm

S¹,

Jatti²,

Batra³

2019

IJECE

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Network on chip (NoC) is a scalable interconnection architecture for every increasing communication demand between many processing cores in system on chip design. Reliability aspects are becoming an important issue in fault tolerant architecture. Hence there is a demand for fault tolerant Agent architecture with suitable routing algorithm which plays a vital role in order to enhance the NoC performance. The proposed fault tolerant Agent based NoC method is used to enhance the reliability and performance of the Multiprocessor System on Chip (MPSoC) design against faulty links and nodes. These agents are placed in hierarchical manner to collect, process, classify and distribute different fault information related to the faulty links and nodes of the network. This fault information is used for further packet routing in the network with the help of shortest path routing algorithm. In addition to this the agent will provide the security for the node by setting firewall, which then decides whether the packet has to be processed or not. This intern provides high performance, low latency NoC by avoiding deadlock and live lock with low area overhead.

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At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs

Cited by 62 publications

References 45 publications

A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures

Design and implementation of secured agent based NoC using shortest path routing algorithm

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