BST is a well established standard and testability framework for digital ICs and boards. The paper presents a test support IC controlled by an IEEE1149.1 interface, capable of providing access to analog nodes in mixed-signal boards. The proposed architecture (ABSINT -Analog to Boundary Scan Interface) is described and relevant implementation issues are discussed. A demonstrator IC implementing the ABSINT architecture is presented, and it is shown how it can be used to provide analog test channels under control of IEEEll49.1.
In this paper, we present an application of the simulation annealing optimization algorithm t o the problem of high-level synthesis of digital systems, targeted to architectures with runtime reconfigurable functional units. The scheduling, allocation and binding problems are treated simultaneously. Reconfiguration times and execution delays are taken into account, along with pipelined execution and precise clock cycles for consumption of each operand.
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