Device physics and design of hetero-gate dielectric tunnel field-effect transistors with different low/high-k EOT ratios

Shih, Chun‐Hsing; Chien, Nguyen Dang; Tran, Huy-Duy; Chuan, Phan Van

doi:10.1007/s00339-019-3246-9

Cited by 6 publications

(4 citation statements)

References 24 publications

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“…In this investigation, −Xsh was set equal to the source length to definitely exclude the effect of a source-side dielectric heterojunction. A low/high-k EOT ratio of 10 was employed (i.e., the dielectric constant of high-k layers is 39) to maximize the on-current enhancement by the HGD engineering (Shih et al, 2020). Firstly, the ambipolar current is still observed in double-gate TFETs, although both the techniques of HGD and low drain doping are used simultaneously.…”

Section: Device Structures and Simulation Modelsmentioning

confidence: 99%

“…In the off-state region, the drain-side dielectric heterojunction helps to suppress the ambipolar current of TFETs, whereas the source-side dielectric heterojunction has no impact on their off-state performance. In the on-state region, while the drain-side dielectric heterojunction indirectly affects the on-current by determining the subthreshold swing, the source-side dielectric heterojunction directly influences the on-current by modulating the on-state tunnel width (Shih et al, 2020). Therefore, the effect of device structure on the role of the source-side dielectric heterojunction is probably different from that on the role of the drain-side dielectric heterojunction.…”

Section: Role Of Source-side Dielectric Heterojunctionmentioning

confidence: 99%

“…However, most studies have used the HGD with the design parameters optimized for a typical TFET (single-gate, silicon, and fixed low/high-k EOTs). Our recent work has shown that the mechanisms of on-current enhancement by source-and drain-side dielectric heterojunctions are basically different (Shih, Chien, Tran, & Chuan, 2020). Furthermore, HGD design depends on the EOT ratio of low-and high-k dielectrics, i.e., different low/high-k EOT ratios require different HGD designs to optimize the on-off switching of TFETs.…”

Section: Introductionmentioning

confidence: 99%

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Different Roles and Designs of Hetero-Gate Dielectric in Single- And Double-Gate Tunnel Field-Effect Transistors

Chien

Vinh

Tham³

et al. 2020

DLU JOS

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Kỹ thuật điện môi cực cổng dị cấu trúc không chỉ giúp giảm dòng lưỡng cực mà còn làm tăng dòng mở của transistor trường xuyên hầm (tunnel field-effect transistr (TFET)). Dựa trên mô phỏng hai chiều, chúng tôi nghiên cứu vai trò và thiết kế của lớp điện môi dị cấu trúc trong TFET đơn và lưỡng cổng. Kết quả cho thấy vai trò và thiết kế của chuyển tiếp điện môi dị cấu trúc phía nguồn trong TFET đơn và lưỡng cổng hầu như giống nhau. Tuy nhiên, vai trò và thiết kế của chuyển tiếp điện môi dị cấu trúc phía máng rất khác nhau trong TFET đơn và lưỡng cổng. Trong cả hai cấu trúc, vị trí tối ưu của chuyển tiếp phía nguồn không phụ thuộc vào tỉ số bề dày ô-xít tương đương của các lớp điện môi có độ điện thẩm cao và thấp. Khi tăng tỉ số này, sự tăng dòng mở nhờ chuyển tiếp phía nguồn đầu tiên tăng (tỉ số < 12) và rồi bão hòa (tỉ số > 12). Đối với chuyển tiếp phía máng, vai trò của nó trong việc tăng dòng mở rất hạn chế trong TFET lưỡng cổng (mọi tỉ số) nhưng lại lớn trong TFET đơn cổng (tỉ số < 12). Khi tỉ số < 12, vị trí tối ưu của chuyển tiếp phía máng trong TFET lưỡng cổng xa cực nguồn hơn 2-3 nm so với trong TFET đơn cổng. Khi tỉ số > 12, vị trí tối ưu của chuyển tiếp phía máng trong TFET lưỡng cổng không phụ thuộc vào tỉ số này, nhưng trong TFET đơn cổng lại phụ thuộc. Những khác biệt trên là do các giếng thế định xứ trong hai cấu trúc có độ sâu khác nhau.

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Section: Device Structures and Simulation Modelsmentioning

confidence: 99%

Section: Role Of Source-side Dielectric Heterojunctionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Different Roles and Designs of Hetero-Gate Dielectric in Single- And Double-Gate Tunnel Field-Effect Transistors

Chien

Vinh

Tham³

et al. 2020

DLU JOS

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show abstract

“…However, the conduction current is considerably lower in TFETs than in MOSFETs because performing the band-to-band tunneling (BTBT) process of carriers is much more difficult than performing their thermal injection [5,6]. Many techniques were proposed to enhance TFET oncurrent, including material and structural methods [7][8][9][10][11]. The proposed solutions were based on exploiting the mechanisms of device physics which are more sophisticated in TFETs than in MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Thin-body effects in double-gate tunnel field-effect transistors

Chien,

Thai,

Shih

2024

J. Phys. D: Appl. Phys.

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Scaling down the body thickness (Tb) of double-gate tunnel field-effect transistors (DG-TFETs) is helpful in suppressing short-channel effects (SCEs), but it may give rise to thin-body effects (TBEs). Based on 2-D device simulations, this study examines the mechanisms and influences of TBEs in DG-TFETs as Tb is scaled down. Differently from previous beliefs, the on-current degradation in thin-body DG-TFETs is not mainly caused by the volume effect, but rather by a newly defined TBE named lateralization effect. This is because the lateralization of tunneling direction significantly increases tunnel width, whereas the reduction of tunneling volume is quite limited due to narrow tunneling regions. To study the Tb-dependence of current, therefore, the vertical tunneling has to be taken into consideration. When considered as a TBE, the fringing field effect caused by reduction in Tb is not significant in degrading the on-current of thin-body DG-TFETs because the narrow tunneling regions are strongly gate-controlled. The only TBE that enhances the on-current is the coupling effect, but its role is only significant for low-bandgap bodies in which the coupling effect can efficiently promote the tunneling towards the body center. Not as previously thought that the quantum confinement effect (QCE) monotonically increased, it even decreases as Tb decreases down to sub-10 nm before turning to increase, thanks to the space sharing between proximate local quantum wells. A comprehensive understanding of the TBEs is useful for providing design insight, especially for determining the optimal Tb to maximize the on-current.

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High‐κ Dielectric Oxides for Electronics

Zhang

Yang

et al. 2021

Oxide Electronics

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Device physics and design of hetero-gate dielectric tunnel field-effect transistors with different low/high-k EOT ratios

Cited by 6 publications

References 24 publications

Different Roles and Designs of Hetero-Gate Dielectric in Single- And Double-Gate Tunnel Field-Effect Transistors

Different Roles and Designs of Hetero-Gate Dielectric in Single- And Double-Gate Tunnel Field-Effect Transistors

Thin-body effects in double-gate tunnel field-effect transistors

High‐κ Dielectric Oxides for Electronics

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