Oxide Electronics 2021
DOI: 10.1002/9781119529538.ch4
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High‐κ Dielectric Oxides for Electronics

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Cited by 3 publications
(2 citation statements)
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“…Non-Local model is used for the region interface of pocket and channel to consider tunneling in lateral direction. As the charges get trapped at oxide/Silicon interface during manufacturing process, material interface specific interface trap model is included with negative trap charge of -4.5×10 10 Coulombs. The designed poc-DG-AJLTFET is simulated for varying gate voltage with drain voltage (V ds ) of 1 V to obtain transfer characteristics, threshold voltage and its performance in subthreshold region.…”
Section: Device Description and Simulationmentioning
confidence: 99%
See 1 more Smart Citation
“…Non-Local model is used for the region interface of pocket and channel to consider tunneling in lateral direction. As the charges get trapped at oxide/Silicon interface during manufacturing process, material interface specific interface trap model is included with negative trap charge of -4.5×10 10 Coulombs. The designed poc-DG-AJLTFET is simulated for varying gate voltage with drain voltage (V ds ) of 1 V to obtain transfer characteristics, threshold voltage and its performance in subthreshold region.…”
Section: Device Description and Simulationmentioning
confidence: 99%
“…In one such investigation, Tunnel field effect transistors (TFETs) came into existence which can produce high switching ratio and steeper subthreshold swing (SS) [5][6][7] . However, Silicon (Si) TFETs with SiO 2 as gate oxide, offer poor electrostatics and experimental results show that the on-state currents in TFETs are typically lower than that of MOSFETs [8][9][10][11] . So, with low on-state current as drawback, new configurations, and materials for TFET are proposed, heterojunction tunnel field effect transistor (HTFET), L and U channel TFETs (LTFET & UTFET) and usage of III-V group materials 12,13 for tunneling devices.…”
mentioning
confidence: 99%