Device parameter changes caused by manufacturing fluctuations of deep submicron MOSFET's

Sitte, Renate; Dimitrijev, Sima; Harrison, H.B.

doi:10.1109/16.333843

Cited by 31 publications

(11 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Different parameters may affect different elements in a clock distribution network. For instance, non-uniformities in the thickness of the gate oxide and imperfections in the polysilicon etching process [5] can cause variations in the current flow within a transistor, thereby affecting the signal delay. Environmentally induced parameter variations caused by changes in the ambient temperature [6] and external radiation [7] also introduce delay variations.…”

Section: Introductionmentioning

confidence: 99%

Parameter variations and crosstalk noise effects on high performance H-tree clock distribution networks

Chanodia

Velenis

2008

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

Controlling the delay and the transition time of the clock signal in the presence of various noise sources, process parameter variations and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. The effects of parameter variations and crosstalk noise on the clock signal propagating along an H-tree clock distribution network are investigated in this paper. In particular, the effects of variations in power supply voltage (V DD ), temperature, and gate oxide thickness (t ox ) on the delay and the transition time of the clock signal are evaluated. Furthermore, the effects of crosstalk between an H-tree structure and other interconnect wires are investigated. Different scenarios of capacitive coupling along different spatial locations of an H-tree are considered. The effects of coupling on the propagation delay, the transition time, and the waveform shape of the clock signal are demonstrated.

show abstract

Section: Introductionmentioning

confidence: 99%

Parameter variations and crosstalk noise effects on high performance H-tree clock distribution networks

Chanodia

Velenis

2008

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…Variations in transistor switching speed [6] can affect the timing characteristics of a register, thereby causing timing constraint violations. Therefore, a system malfunction may occur, not only due to uncertainty in the signal propagation delay, but also due to variations of the timing characteristics within a register.…”

Section: Introductionmentioning

confidence: 99%

Effects of process and environmental variations on timing characteristics of clocked registers

Roberts

Velenis

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

Violations of the timing constraints in a clocked register can cause a synchronous system to malfunction. The effects of parameter variations on the timing characteristics of registers that determine the timing constraints are investigated in this paper. The sensitivity of the setup time and data propagation delay to variations in power supply voltage, temperature, and gate oxide thickness is demonstrated for four different register designs. Furthermore, design modifications are proposed that enhance the robustness of each register to variation effects.

show abstract

“…To work towards the continuing improvement of performance and density of ULSI technology MOSFET devices are scaled down to sub-0.1 lam dimensions. It results in a decreasing number of channel impurities whose random distribution leads to significant fluctuations of threshold voltage and off-state leakage current [1] which are likely to induce serious consequences on the operation and performance of logical and analog circuits [2]. For such dimensions of active region, impurities cannot be anymore considered as a doping continuum.…”

Section: Introductionmentioning

confidence: 99%

An lonised-impurity Scattering Model for 3D Monte Carlo Device Simulation with Discrete Impurity Distribution

et al. 2001

View full text Add to dashboard Cite

An improved 3-D Monte Carlo simulation model is developed to treat the discrete random dopant distribution in sub-0.1 gm MOSFET. The new atomistic model is based on a scattering rate calculation and an algorithm that take into account many-body effects and the local variations of screening length according to impurity distribution and bias conditions.To validate this new approach low field electron drift mobility and diffusion coefficient have been computed using simulation of 3D bars for 1015-1018 cm-3 range of average doping concentration. A good agreement is found between calculation and experimental mobility data at 300 K.

show abstract

Device parameter changes caused by manufacturing fluctuations of deep submicron MOSFET's

Cited by 31 publications

References 7 publications

Parameter variations and crosstalk noise effects on high performance H-tree clock distribution networks

Parameter variations and crosstalk noise effects on high performance H-tree clock distribution networks

Effects of process and environmental variations on timing characteristics of clocked registers

An lonised-impurity Scattering Model for 3D Monte Carlo Device Simulation with Discrete Impurity Distribution

Contact Info

Product

Resources

About