Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform

Maheshwaram, Satish; Manhas, S. K.; Kaushal, Gaurav; Bulusu, Anand; Singh, Navab

doi:10.1109/led.2012.2197592

Cited by 7 publications

(5 citation statements)

References 9 publications

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“…Studies on basic standard cells like inverter have also been done [11]. However, since standard cells use a large variety of layout structures, it would be difficult to evaluate the layout efficiency of a complete vertical channel standard cell library without using a systematic framework.…”

Section: B Related Workmentioning

confidence: 99%

“…Recent studies on vertical devices have demonstrated the improved fabrication process control and many appealing properties [9,10]. Arrays of VGAA with 20nm diameter have been successfully fabricated, and good transistor characteristics such as large drive current, high Ion/I of f ratio, delay improvement [11], and better short channel effect control of VGAA have been observed [2], showing the potential opportunities provided by VGAA for the continued scaling of semiconductor devices.…”

Section: Introductionmentioning

confidence: 98%

“…Many vertical structures have been studied and discussed [11,12,15]. Unlike planar transistors, the current flow of vertical channel FETs is perpendicular to the wafer plane, which brings new challenges to efficient layout generation.…”

Section: A Introduction To Vertical Fetsmentioning

confidence: 99%

“…Contacts are connected to the top, bottom, and gate of the vertical pillar. Note that the gate extension can be aligned with the bottom and top contact plane [11] as shown in Figure 1 (a), or be perpendicular to the bottom and top contact plane [12] as shown in the 2D layout in Figure 1 (b). The efficient layout generation proposed in this paper is applicable to both vertical structures.…”

Section: A Introduction To Vertical Fetsmentioning

confidence: 99%

“…Interested readers may refer to [11,18] for some early studies. In this paper, we neglect the overall possible benefits of vertical channel devices by comparing the area using same effective width with lateral channel devices.…”

Section: A Introduction To Vertical Fetsmentioning

confidence: 99%

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Efficient Layout Generation and Design Evaluation of Vertical Channel Devices

Wang

Gupta

2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Vertical gate-all-around (VGAA) has been shown to be one of the most promising devices for the scaling beyond 10nm for its reduced delay, large driving current, and good gate control. Moreover, emerging devices such as heterojunction tunneling FETs are more amenable to vertical fabrication. However, past studies of vertical channel devices focused more on regular memory architectures and simple standard cells like inverter. Since naive migration of regular FinFET layouts to vertical FETs yields little benefits, we identify several vertical efficient layout structures and propose novel layout generation heuristics for vertical channel devices. We also compare VGAA with symmetric and asymmetric source/drain architectures. The layout efficiencies of several VGAA structures, vertical double gate (VDG), lateral gate-all-around (LGAA), and FinFET are presented in our experiments. We observe that even though most vertical channel standard cells have more diffusion gaps than lateral cells do, they still benefit from vertical architectures in area because of the elimination of diffusion contacts. For asymmetric architectures, the area is larger than symmetric architectures because of the extra diffusion gaps needed, but our experiments indicate that for both symmetric and asymmetric architectures, vertical channel devices are likely to have a density advantage over lateral channel devices assuming that current drive strengths of both are similar.

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Section: B Related Workmentioning

confidence: 99%