Device-architecture co-optimization of STT-RAM based memory for low power embedded systems

Xu, Jun; Niu, Ji-rui; Zhu, Wanxue; Kang, Alice J.; Nowak, Bernadeta; Xie, Weibo

doi:10.1109/iccad.2011.6105369

Cited by 29 publications

(24 citation statements)

References 23 publications

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“…Prior work experimented with aggressive STT-RAM pulse durations as low as 2-3ns [27], [56], [63]. Shorter write pulses require higher write current densities, which not only can lead to potential thermal issues (that may further be exacerbated by locality), but also require larger write amplifiers.…”

Section: Sensitivity Analysis and Comparison To Pcrammentioning

confidence: 99%

Evaluating STT-RAM as an energy-efficient main memory alternative

Kültürsay

Kandemir

Sivasubramaniam

et al. 2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

382

212

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Abstract-In this paper, we explore the possibility of using STT-RAM technology to completely replace DRAM in main memory. Our goal is to make STT-RAM performance comparable to DRAM while providing substantial power savings. Towards this goal, we first analyze the performance and energy of STT-RAM, and then identify key optimizations that can be employed to improve its characteristics. Specifically, using partial write and row buffer write bypass, we show that STT-RAM main memory performance and energy can be significantly improved. Our experiments indicate that an optimized, equal capacity STT-RAM main memory can provide performance comparable to DRAM main memory, with an average 60% reduction in main memory energy.

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Section: Sensitivity Analysis and Comparison To Pcrammentioning

confidence: 99%

Evaluating STT-RAM as an energy-efficient main memory alternative

Kültürsay

Kandemir

Sivasubramaniam

et al. 2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

382

212

View full text Add to dashboard Cite

show abstract

“…The waveform of the switching current, I c , is determined by I c0 and the pulse width [6], [21], and when the pulse duration is on the order of a few nanoseconds, I c ≈ I c0 . Since the amount of current that a transistor can drive is directly proportional to its width W T X , it follows that…”

Section: B Relating Bit Cell Area To Thermal Stabilitymentioning

confidence: 99%

Improving STT-MRAM density through multibit error correction

Bel

Kim

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-STT-MRAMs are prone to data corruption due to inadvertent bit flips. Traditional methods enhance robustness at the cost of area/energy by using larger cell sizes to improve the thermal stability of the MTJ cells. This paper employs multibit error correction with DRAM-style refreshing to mitigate errors and provides a methodology for determining the optimal level of correction. A detailed analysis demonstrates that the reduction in nonvolatility requirements afforded by strong error correction translates to significantly lower area for the memory array compared to simpler ECC schemes, even when accounting for the increased overhead of error correction.

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“…Calculation shows that combination (3) offers us the smallest STT-RAM array area, which is only 88 % and 95 % of the ones of (1) and (2), respectively. We note that PS3-RAM can be seamlessly embedded into the existing deterministic memory macro models [31] for the extended capability on the statistical reliability analysis and the multi-dimensional design optimizations on area, yield, performance and energy. Figure 14 illustrates the STT-RAM design space in terms of the combinations of Y wr , W, T w and ECC scheme.…”

Section: Array Level Analysis and Design Optimizationmentioning

confidence: 99%