Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications

Tripathy, Manas Ranjan; Singh, Ashish Kumar; Samad, A; Chander, Sweta; Baral, Kamalaksha; Singh, Prince Kumar; Jit, Satyabrata

doi:10.1109/ted.2020.2964428

Cited by 110 publications

(42 citation statements)

References 33 publications

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“…In previous research, the advanced bandgap-engineered TaN/Al 2 O 3 /HfO 2 /SiO 2 /Si (BE-TAHOS) structure has been investigated for a faster erasing speed and larger memory window by incorporating Si 3 N 4 at the tunneling oxide layer [37][38][39][40][41][42][43][44]. By utilizing this BE-TAHOS structure [34][35][36] and applying Al 2 O 3 at the tunneling layer, the advanced structure of TaN/Al 2 O 3 /HfO 2 /SiO 2 /Al 2 O 3 /SiO 2 /Si (TAHOAOS) is designed for NOR flash memory.…”

Section: Device Structure and Model Physics 21 Structure Of The Promentioning

confidence: 99%

“…Consequently, it has been demonstrated that the retention characteristics can be significantly improved in a high-κ-based NOR flash memory device by utilizing the advanced tunneling layers with SiO 2 /Al 2 O 3 /SiO 2 on the tunnel field effect transistor (TFET) structure, which has been broadly studied for low power application [37][38][39][40][41][42][43][44]. From an array perspective, it has been demonstrated that the proposed memory device structure is also able to inhibit the programming in unselected cells by bottom gate effect.…”

Section: Introductionmentioning

confidence: 99%

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Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Song

Park

2021

Micromachines

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For improving retention characteristics in the NOR flash array, aluminum oxide (Al2O3, alumina) is utilized and incorporated as a tunneling layer. The proposed tunneling layers consist of SiO2/Al2O3/SiO2, which take advantage of higher permittivity and higher bandgap of Al2O3 compared to SiO2 and silicon nitride (Si3N4). By adopting the proposed tunneling layers in the NOR flash array, the threshold voltage window after 10 years from programming and erasing (P/E) was improved from 0.57 V to 4.57 V. In order to validate our proposed device structure, it is compared to another stacked-engineered structure with SiO2/Si3N4/SiO2 tunneling layers through technology computer-aided design (TCAD) simulation. In addition, to verify that our proposed structure is suitable for NOR flash array, disturbance issues are also carefully investigated. As a result, it has been demonstrated that the proposed structure can be successfully applied in NOR flash memory with significant retention improvement. Consequently, the possibility of utilizing HfO2 as a charge-trapping layer in NOR flash application is opened.

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Section: Device Structure and Model Physics 21 Structure Of The Promentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Song

Park

2021

Micromachines

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“…In the view of fabrication, the VTFET is easier to manufacture than the conventional TFETs [ 16 , 17 , 18 , 19 , 20 ]; the top–down nanofabrication technology can be used in VTFET, which enables precise control over the physical dimensions of the nanowires as well as the size and configuration [ 21 , 22 ]. Moreover, the number of pads could be scaled up to thousands.…”

Section: Introductionmentioning

confidence: 99%

Study of a Gate-Engineered Vertical TFET with GaSb/GaAs0.5Sb0.5 Heterojunction

et al. 2021

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It is well known that the vertical tunnel field effect transistor (TFET) is easier to fabricate than the conventional lateral TFETs in technology. Meanwhile, a lightly doped pocket under the source region can improve the subthreshold performance of the vertical TFETs. This paper demonstrates a dual material gate heterogeneous dielectric vertical TFET (DMG-HD-VTFET) with a lightly doped source-pocket. The proposed structure adopts a GaSb/GaAs0.5Sb0.5 heterojunction at the source and pocket to improve the band-to-band tunneling (BTBT) rate; at the same time, the gate electrode is divided into two parts, namely a tunnel gate (M1) and control gate (M2) with work functions ΦM1 and ΦM2, where ΦM1 > ΦM2. In addition, further performance enhancement in the proposed device is realized by a heterogeneous dielectric corresponding to a dual material gate. Simulation results indicate that DMG-HD-VTFET and HD-VTFET possess superior metrics in terms of DC (Direct Current) and RF (Radio Frequency) performance as compared with conventional VTFET. As a result, the ON-state current of 2.92 × 10−4 A/μm, transconductance of 6.46 × 10−4 S/μm, and average subthreshold swing (SSave) of 18.1 mV/Dec at low drain voltage can be obtained. At the same time, DMG-HD-VTFET could achieve a maximum fT of 459 GHz at 0.72 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 35 GHz at Vgs = 0.6 V, respectively. So, the proposed structure will have a great potential to boost the device performance of traditional vertical TFETs.

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“…So, ambipolar analysis 26 in drain current modeling is extremely important and included in the proposed drain current model. The earlier study 9 is unable to focus on device characteristics at sub 10 nm body thickness which is extremely important to improve I ON / I OFF ratio 27 for low power VLSI application 28,29 …”

Section: Introductionmentioning

confidence: 99%

“…The earlier study 9 is unable to focus on device characteristics at sub 10 nm body thickness which is extremely important to improve I ON /I OFF ratio 27 for low power VLSI application. 28,29 Thus, in this manuscript, first time a quasi-analytical model of a silicon p-channel DMG TFET has been developed incorporating device physics to determine surface potential and non-local drain current with ambipolar characteristics. The developed model is also efficient to capture the device performances at sub 10 nm body thickness including quantum confinement.…”

Section: Introductionmentioning

confidence: 99%

A dual gate material tunnel field effect transistor model incorporating two‐dimensional Poisson and Schrodinger wave equations

Mohanty

Dutta

Das

2021

Int J Numerical Modelling

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This paper presents an accurate analytical model of surface potential and drain current for a long channel dual material gate (DMG) tunneling field‐effect transistor (TFET) with the addition of nonlinear inversion charge developed at the channel/drain interface region, ambipolar characteristic, and quantum confinement. The model includes the effect of dual metal gate work function as it controls the threshold voltage without considering a fully depleted undoped channel region. The current model includes the effect of charge accumulation at the interface of two gates and an appropriate mathematical expression of nonlinear inversion charge developed at the interface of two gates has been derived from the two‐dimensional (2D) Schrodinger wave equation incorporating quantum confinement. The model is effective to capture transfer characteristics at Sub 10 nm body thickness. A high ION/IOFF ratio and less than 27 mV/decade subthreshold swing are achieved at 2 nm body thickness which is desirable for low power VLSI application. The proposed model has been compared and calculated by Sentaurus TCAD with fair accuracy and a good resemblance, including ambipolar characteristics at sub 10 nm body thickness has been achieved.

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Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications

Cited by 110 publications

References 33 publications

Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Study of a Gate-Engineered Vertical TFET with GaSb/GaAs0.5Sb0.5 Heterojunction

A dual gate material tunnel field effect transistor model incorporating two‐dimensional Poisson and Schrodinger wave equations

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