Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Abstract

In recent years, subthreshold operation has gained a lot of attention due to ultra low-power consumption in applications requiring low to medium performance. It has also been shown that by optimizing the device structure, power consumption of digital subthreshold logic can be further minimized while improving its performance. Therefore, subthreshold circuit design is very promising for future ultra low-energy sensor applications as well as high-performance parallel processing. This paper deals with various device and circuit design challenges associated with the state of the art in optimal digital subthreshold circuit design and reviews device design methodologies and circuit topologies for optimal digital subthreshold operation. This paper identifies the suitable candidates for subthreshold operation at device and circuit levels for optimal subthreshold circuit design and provides an effective roadmap for digital designers interested to work with ultra low-power applications.

Design & Analysis of Single Bit Sub-Threshold Sram Using Dtmos with Traditional Sram Design under 32nm Design

“…Dynamic threshold metal oxide CMOS ©IJRASET (UGC Approved Journal): All Rights are Reserved (DTMOS) techniques, consisting of positive feedback loop is acts as a bistable latch [6,7]. So the circuit stability can be improved [5][6][7][8][9]. Optimal characteristics & performance is obtained below the threshold region, with a supply voltage is less than the threshold voltage ,called sub threshold operation with a functional approach through read, write operations & Performance by power and delay is characterized A High Vth & low Vth transistor [6][7][8]are used to reduce the leakage power and Finally performance is estimated by static and dynamic power along with delay.…”

Subthreshold Energy Harvesters Circuits for Biomedical Implants Applications

“…[9] As shown in the Fig. 2, dynamic voltage dominates with higher power supply voltages in many of today's circuit designs.…”

“…For energy constrained applications such as medical devices (like pacemaker, cochlear implants, wearable computing implants), wireless sensors, and energy harvesting circuits in which lower power consumption and extended battery lifetime is of concern, subthreshold circuits may be a good alternative. [9] Fig . 6 illustrates the Ids vs, Vds subthreshold output characteristics curve of nmos with varying Vgs from 0.2 to 0.5.…”

Analytical Model of Double Gate MOSFET for High Sensitivity Low Power Photosensor

“…Since MOSFET has very low off current as compared to other conventional devices thus low off current implies small dark current thus enhanced sensitivity for photo detection. Apart from high sensitivity, operating device in subthreshold region has the advantage of low power consumption [38,39] thus it helps in realizing the concept of low power highly sensitive sensors and also compatible with CMOS integration. In that sense DG MOSFET is even better than bulk MOSFET because of further lower off current due to effective gate control [39,40].…”