Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS

2016

Microsyst Technol

Section: Simulation Results and Discussionmentioning

confidence: 99%

Low-power half-select free single-ended 10 transistor SRAM cell

Sinha

2016

Microsyst Technol

“…Monte Carlo (MC) simulations are performed for the estimation. L (channel length), W (width), and t ox (oxide thickness), u 0 (zero bias carrier mobility) and R Ƒ (sheet resistance of source/drain diffusion) are assumed to have independent Gaussian distributions with 3ı variation of 10% [16], [17]. The temperature is varied within the range from 24 °C to 134 °C using absolute Gaussian function.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

Low Active Power High Speed Cache Design

2011 International Symposium on Electronic System Design

Kafeel

Imran

et al. 2011

The active power is one of the major contributors to the total power consumption in the SRAM cell. It consists mainly of two components -write power and read power. These power dissipations occur due to charging/discharging of large bitline capacitance. On-chip cache size has become increasingly important for high performance applications, and it now presents more of a limit to microprocessor speed than clock rate. The models and methodologies for the design of SRAM, an integral component of microprocessor cache, have changed with time. Presently, continued scaling is threatened by variability in SRAM performance and function. This work addresses the emerging threat of variability keeping active power consumption and speed of operation in consideration.Keywords-Active power; variability; static random access memory (SRAM); read static noise margin (RSNM); carbon nanotube field effect transistor (CNFET); chirality vector.

“…The various process parameters including L, NDEP, t ox and V t are assumed to have independent Gaussian distributions with a 3σ variation of 10%, to follow projected trends [30].…”

Section: Simulation Setupmentioning

confidence: 99%

Circuit‐level design technique to mitigate impact of process, voltage and temperature variations in complementary metal‐oxide semiconductor full adder cells

Dokania

IET Circuits, Devices & Systems

2015

Modern digital circuits are facing aggressive technology and voltage scaling under emerging technology generations. This study proposes a circuit-level technique to mitigate the adverse effects of process, voltage and temperature (PVT) variations on the design metrics of full adder (FA) cells under such ultra-deep sub-micron technology nodes. The proposed FA cells exhibit improved variability because of the use of inverting low voltage Schmitt trigger sub-circuits incorporated in the designs in place of inverters. The proposed circuits have been designed to operate in the near-threshold region, which offers a trade-off between performance and power consumption. The comparative analysis based on Monte Carlo simulations in a SPICE environment, using the 16-nm complementary metal-oxide semiconductor predictive technology model, demonstrates that the proposed technique is capable of mitigating the impact of PVT variations on major design metrics such as power, delay and powerdelay product in FA cells. This improvement is achieved at the expense of two extra transistors for every replaced inverter in the FA cell.