Development of Pulse Transfer Circuits for Serially Biased SFQ Circuits Using the Nb 9-Layer 1-$\mu\hbox{m}$ Process

Ehara, K.; Takahashi, Akitomo; Yamanashi, Yuki; Yoshikawa, Nobuyuki

doi:10.1109/tasc.2012.2233535

Cited by 9 publications

(3 citation statements)

References 9 publications

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“…In order to make sure that the calibrated parameters deliver reasonable results for mutual inductance, we therefore modelled structures from earlier publications for which measurements were reported. Firstly, we recalculated the four coupling structures in [8] with the calibrated parameter set, and compared the results with those obtained with nominal parameters [23]. The coupling values are shown in table 5, and even though the measured coupling structures were made in an earlier fabrication run, which means that parameter deviations for the specific run were not calibrated, the results with the calibrated parameter set are on average the same or better than calculations with nominal parameters.…”

Section: Coupling Structures From Earlier Publicationsmentioning

confidence: 99%

“…Increasingly complex circuits, such as robustly shielded serially biased circuits [8], require layout verification and inductance extraction that takes the many layers and vertical nature of vias into account. Experimental measurements of the inductance of stacked vias have been reported [9], but this is of limited usefulness when vias pass through ground planes (GPs) or when vias form part of inductive structures with ground current return paths that differ from those used in the measurements.…”

Section: Introductionmentioning

confidence: 99%

“…Calculated and measured coupling coefficient k of several magnetic coupling structures of SFQ pulse transfer circuits[8].…”

mentioning

confidence: 99%

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Fast and accurate inductance and coupling calculation for a multi-layer Nb process

Fourie

Takahashi

Yoshikawa

2015

Supercond. Sci. Technol.

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Currently, fabrication processes for superconductive integrated circuits are moving to multiple wiring and shielding layers, some of which are placed below the main ground plane (GP) and device layers. The Advanced Industrial Science and Technology advanced process (ADP2) was the first such multi-layer Nb process with planarized passive transmission line and GP layers below the junction layer, and is at the time of writing still the most developed. This process allows complex circuit designs, and accurate inductance extraction helps to push the boundaries of the layouts possible. We show that the position of ground connections between ground layers influences the inductance of structures for which these GPs act as return path, and that this needs to be accounted for in modelling. However, due to the number of wiring layers and GPs, full layout modelling of large cells causes long calculation times. In this paper we discuss methods with which to reduce model size, and calibrate InductEx calculations using these methods against measured results. We show that model reduction followed by calibration results in fast calculation times while good accuracy is maintained. We also show that InductEx correctly handles coupling between conductors in a multi-layer layout, and how to model layouts to gauge unwanted coupling between power lines and single flux quantum electronics.

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Section: Coupling Structures From Earlier Publicationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Fast and accurate inductance and coupling calculation for a multi-layer Nb process

Fourie

Takahashi

Yoshikawa

2015

Supercond. Sci. Technol.

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Superconducting Electronics

Fourie

2014

Wiley Encyclopedia of Electrical and Electronics Engineering

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An overview of the state of superconducting electronics is presented, starting with Josephson junction and dc SQUID as active devices. Analogue electronics for detectors, mixers, voltage standards and ultra‐sensitive magnetometers are discussed, as well as their application to fields ranging from radio astronomy through metrology to stand‐off security imaging. An overview of the fundamental operating principles of the most successful superconducting logic family, RSFQ, is given, followed by a critical look at the main problems facing large‐scale RSFQ integrated circuits. Contemporary methods to reduce static power consumption and magnetic fields from bias currents are highlighted, with a quick look at energy‐efficient SFQ (eSFQ), current recycling and on‐chip shielding in advanced fabrication processes as prime examples of such methods. Integrated circuit fabrication, cryocooling and other digital logic families are also discussed. We conclude with a look at energy‐efficient supercomputing and quantum computing as near‐future applications of superconducting electronics.

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Optimization of SFQ Logic Gate Considering Dependence of its Signal Propagation Delay on the Bias Voltage

2014

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Development of Pulse Transfer Circuits for Serially Biased SFQ Circuits Using the Nb 9-Layer 1-$\mu\hbox{m}$ Process

Cited by 9 publications

References 9 publications

Fast and accurate inductance and coupling calculation for a multi-layer Nb process

Fast and accurate inductance and coupling calculation for a multi-layer Nb process

Superconducting Electronics

Optimization of SFQ Logic Gate Considering Dependence of its Signal Propagation Delay on the Bias Voltage

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