Development of 3D silicon module with TSV for system in packaging

Khan, N.; Rao, V.S.; Lim, S.; We, Ho Soon; Lee, V.; Wu, Zhang Xiao; Yang, Rui; Liao, E.B.

doi:10.1109/ectc.2008.4550027

Cited by 73 publications

(25 citation statements)

References 3 publications

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“…3D packaging using micro bumps and Through Silicon Vias (TSV) is emerging packaging technology to overcome the shortcoming. [2,3] Chip-to-chip stacking using conventional package assembly method / tools is the most cost-effective way of making 3D-Packages. But fine pitch (100um) and low standoff interconnections between multiple-chips by single re-flow is challenging.…”

Section: Introductionmentioning

confidence: 99%

Three chips stacking with low volume solder using single re-flow process

Khan

Wee

Chiew

et al. 2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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Miniaturized 3D package with shorter distances between chips are needed for the mobile and high frequency applications. Chip-to-chip stacking for 3D packaging using conventional assembly method and single step reflow attachment is the most cost-effective. But fine pitch microjoints of stacked chip by single re-flow attachment is challenging due to chip movement during stacking processes, which lead to poor assembly yields. This paper reports a method of stacking chips by thermal tacking and permanent joints are formed simultaneously by single re-flow step.

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Section: Introductionmentioning

confidence: 99%

Three chips stacking with low volume solder using single re-flow process

Khan

Wee

Chiew

et al. 2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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“…The benefits of 3D integration with TSV technology for future ICs include reduced interconnection delay due to shorter chip to chip interconnection lengths, smaller die size which is motivated by the portable and hand held applications, and ability to use distinct, even heterogeneous technologies (analog, logic, RF, MEMS, SiGe, III-V) on separate vertically interconnected layers to build complex systems [1][2][3][4][5][6][7][8][9][10][11][12][13]. In the new applications (such as Bio, MEMS, Optical, and RF devices), the vertical integration requires a low processing temperature below 200°C to bond these devices without degrading their performance.…”

Section: Introductionmentioning

confidence: 99%

A low stress bond pad design for low temperature solder interconnections on through silicon vias (TSVs)

Zhang

Rajoo

Selvanayagam

et al. 2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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Low temperature bonds are thin intermetallic bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints comprised completely of intermetallic compounds, will fail in a sudden unexpected manner, compared to normal solder joints which fail in a ductile manner where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above through-silicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion (CTE) causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress on post-formation cooling to room temperature increases the likelihood of joint failure.This paper presents a novel pad design to overcome the situation of high stress in the joints. The proposed design does not involve any additional fabrication or material cost. Simulation results show that with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also done in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance and higher shear strength than the samples with the usual pad design. Introduction3D chip-stacking technology with TSVs is the next generation integration technology for IC packaging. The benefits of 3D integration with TSV technology for future ICs include reduced interconnection delay due to shorter chip to chip interconnection lengths, smaller die size which is motivated by the portable and hand held applications, and ability to use distinct, even heterogeneous technologies (analog, logic, RF, MEMS, SiGe, III-V) on separate vertically interconnected layers to build complex systems [1][2][3][4][5][6][7][8][9][10][11][12][13]. In the new applications (such as Bio, MEMS, Optical, and RF devices), the vertical integration requires a low processing temperature below 200°C to bond these devices without degrading their performance. The current method uses higher temperature of more than 300°C for bonding and interconnecting the different devices or wafers in the vertical fashion [8]. A high bonding temperature degrades the performance and sensitivity of the Bio, MEMS, Optical, and RF devices. Therefore, a low temperature bonding at less than 200°C is a must for vertically integrating the different systems such as multifunctional devices into a system in package.

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“…The follow-up board vibrations begin to develop in the first tens of milliseconds and will even exaggerate the solder yielding due to escalated and repeated amplitude in the peeling stress whose magnitude can be far larger than the solder's yielding strength. As 3D stacking technology such as the package-onpackage (PoP) assembly [3] is emerging [4,5], it is desirable to understand its drop-impact response and reliability. Lai et al showed that the drop reliability of a double-layer PoP assembly is determined by the critical solders at the ball-out level [6].…”

Section: Introductionmentioning

confidence: 99%

Failure Mechanism of stacked CSP module under board-level drop impact

Narravula

Chen

Peterson

2009

2009 59th Electronic Components and Technology Conference

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Riding chip scale packages (CSPs) in the z-direction enables high-density 3D electronic packaging in which the shorter, through-interposer interconnections can provide faster signal transmission and integrity. Successful applications of such 3D stacking packages require a better understanding of their mechanical responses to and reliability under various loading conditions. In this paper, we present analysis results for failure mechanisms of 3D packaging by (1) simulating detailed mechanical response of the critical joints to a board-level drop impact and identifying the possible failure modes and mechanisms of 95.5Sn4AgCu (SAC) solder joints in 3D stacked-CSP modules under drop impact, and (2) building a theoretical framework that estimates impact-induced stresses in the critical solders. The results suggest the following: (1) Stresses predicted by the theoretical models are on the same order of magnitude as numerical results. (2) Both the theoretical and numerical results show that stresses fluctuate at a higher frequency and are about one order of magnitude smaller in the 90° orientation drop than in the 0° drop. The latter implies that all the stack-like 3D packaging reacts dynamically "stiffer" in the 90° drop scheme. This explains why the 0° drop scheme is the most critical test; if a specimen can survive from the 0° drop test, it should survive a drop test in any other orientation. (3) The FE results display uneven deformation among the solders of the stack CSP module, in particular in the 0° orientation drop. We deduce that the unequal deformation among the solders, due to differential flexure between the board and the packages, is the main cause for such high stresses in the critical solders in the 0° drop. Solders carry impact load more equally and react stiffer in the 90° orientation drop, resulting in much smaller stresses.

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Development of 3D silicon module with TSV for system in packaging

Cited by 73 publications

References 3 publications

Three chips stacking with low volume solder using single re-flow process

Three chips stacking with low volume solder using single re-flow process

A low stress bond pad design for low temperature solder interconnections on through silicon vias (TSVs)

Failure Mechanism of stacked CSP module under board-level drop impact

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