Three chips stacking with low volume solder using single re-flow process

With the trend of microelectronics packaging toward more functionality, high performance and smaller form factor, the product is required to deliver more I/Os and better electrical characteristics under a minimum module system. Therefore, a 3D IC integration System in Package (SiP) with passive Through Silicon Via (TSV) interposer technology is proposed to provide high density and heterogeneous integration needed for such requirement.Due to the Coefficients of Thermal Expansion (CTE) mismatch between materials, thermal-mechanical stress and warpage are induced during Through Silicon Interposer (TSI) fabrication process, which may affect TSV crack or Controlled Collapse Chip Connection (C4) bump crack after TSI bonding to organic substrate process. Therefore, this work is a step by step process simulation with various design parameters by finite element method (FEM) to investigate stress and warpage behaviors of processing effect. For both full array dummy bumps layout and thinner top chips are to reduce micro-bump stress. Also, low CTE organic substrate core, high CTE mold compound and thinner top chips perform lower package warpage. Finally, this paper aims to provide a guideline to designer for 3D IC integration SiP with passive TSV interposer structure by using the finite element models. IntroductionAs the demands of more functionality and high performance, the product is required to deliver more I/Os and better electrical characteristics. Therefore, a 3D IC integration package with TSI technology is proposed to provide high density and heterogeneous integration needed for such requirement. Functional chips stacked on a TSI then assembled on an organic substrate is as test vehicle (See Figure-1). The electrical connection between functional chips to TSI is through micro-bumps and Re-Distribution Layer (RDL) then is going to the TSV of TSI. TSI and organic substrate interconnect is by C4 bumps. Due to the CTE mismatch between materials, thermal-mechanical stress and warpage are induced during TSI fabrication and package assembly process, which may affect TSV crack or C4 bump crack after top chips bonding to TSI and TSI bonding to organic substrate processes.Firstly, the design parameters including RDL design, TSI thickness, bump layout, top chip thickness and DRAM chips space are discussed in detail. The key challenge during assembly process is chip level warpage contribution to cause

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Three chips stacking with low volume solder using single re-flow process

Cited by 8 publications

References 7 publications

Overview of Bonding and Assembly for 3D Integration

Overview of Bonding and Assembly for 3D Integration

3D Integration

Development of Through Silicon Via (TSV) interposer for memory module flip chip package

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