A low stress bond pad design for low temperature solder interconnections on through silicon vias (TSVs)

Abstract

Low temperature bonds are thin intermetallic bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints comprised completely of intermetallic compounds, will fail in a sudden unexpected manner, compared to normal solder joints which fail in a ductile manner where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above through-silicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion (CTE) causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress on post-formation cooling to room temperature increases the likelihood of joint failure.This paper presents a novel pad design to overcome the situation of high stress in the joints. The proposed design does not involve any additional fabrication or material cost. Simulation results show that with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also done in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance and higher shear strength than the samples with the usual pad design. Introduction3D chip-stacking technology with TSVs is the next generation integration technology for IC packaging. The benefits of 3D integration with TSV technology for future ICs include reduced interconnection delay due to shorter chip to chip interconnection lengths, smaller die size which is motivated by the portable and hand held applications, and ability to use distinct, even heterogeneous technologies (analog, logic, RF, MEMS, SiGe, III-V) on separate vertically interconnected layers to build complex systems [1][2][3][4][5][6][7][8][9][10][11][12][13]. In the new applications (such as Bio, MEMS, Optical, and RF devices), the vertical integration requires a low processing temperature below 200°C to bond these devices without degrading their performance. The current method uses higher temperature of more than 300°C for bonding and interconnecting the different devices or wafers in the vertical fashion [8]. A high bonding temperature degrades the performance and sensitivity of the Bio, MEMS, Optical, and RF devices. Therefore, a low temperature bonding at less than 200°C is a must for vertically integrating the different systems such as multifunctional devices into a system in package.

Chip Warpage Induced by Tapered Through-Silicon Vias: A Numerical Analysis

“…Thermal stresses in the TSV structure have been extensively studied [1][2][3][4][5][6][7][8][9][10]. Much less attention has been directed to the effect of a tapered TSV geometry, which is commonly made during wafer fabrication [7,[11][12][13][14]. Tapered TSVs not only give rise to thermal stresses (just like the case of straight TSVs) but also cause shape changes of the wafer (unlike straight TSVs), namely chip warpage.…”