Design and fabrication of a reliability test chip for 3D-TSV

Trigg, A. D.; Yu, Li; Zhang, Xiaowu; Chong, Chai Tai; Kuo, Chun-Chi; Khan, N.; Yu, Daquan

doi:10.1109/ectc.2010.5490889

Cited by 25 publications

(9 citation statements)

References 23 publications

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“…It can result in voids that eventually lead to open circuits. This wear-out mechanism can also be a major reliability issues for TSVs [1][2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Resistance increase due to electromigration induced depletion under TSV

Frank

Chappaz

Leduc

et al. 2011

2011 International Reliability Physics Symposium

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“…It can result in voids that eventually lead to open circuits. This wear-out mechanism can also be a major reliability issues for TSVs [1][2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Resistance increase due to electromigration induced depletion under TSV

Frank

Chappaz

Leduc

et al. 2011

2011 International Reliability Physics Symposium

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“…It has been reported in the literature that a TSV can handle a current density higher than 70,000 A/cm 2 [108]. Published work on TSV reliability screening indicates that a sustained current density of 15,000 A/cm 2 is possible through a TSV without damage [109].…”

Section: Simulation Resultsmentioning

confidence: 99%

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Noia

Chakrabarty

2014

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As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects have become the dominant contributor to circuit delay and a significant component of power consumption. In order to reduce the length of these interconnects, 3D integration and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry. 3DSICs not only have the potential to reduce average interconnect length and alleviate many of the problems caused by long global interconnects, but they can offer greater design flexibility over 2D ICs, significant reductions in power consumption and footprint in an era of mobile applications, increased on-chip data bandwidth through delay reduction, and improved heterogeneous integration.Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a die stack, are a source of additional and unique defects not seen before in ICs. At the same time, testing these TSVs, especially before die stacking, is recognized as a major challenge.The testing of a 3D stack is constrained by limited test access, test pin availability, power, and thermal constraints. Therefore, efficient and optimized test architectures are needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively expensive.Methods of testing TSVs prior to bonding continue to be a difficult problem due to test access and testability issues. Although some built-in self-test (BIST) techniques have been proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through iv TSV probing. This has the benefit of not needing large analog test components on the die, which is a significant drawback of many BIST architectures. Coupled with an optimization method described in this dissertation to create parallel test groups for TSVs, test time for pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.The addition of boundary registers on functional TSV paths required for pre-bond probing results in an increase in delay on inter-die functional paths. This cost of test architecture insertion can be a significant drawback, especially considering that one benefit of 3D integration is that critical paths can be partitioned between dies to reduce their delay. This dissertation derives a retiming flow that is used to recover the additional delay added to TSV paths by test cell insertion.Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary during 3D-SIC manufacturing. To reduce test cost, the test architecture and test scheduling for the stack must be optimized to reduce test time across all necessary test insertions. This dissertation exam...

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“…This too stems from the fundamental mismatch of CTE's between TSV metallization such as copper, and the surrounding silicon envelope. Several researchers have studied various aspects of this problem [56][57][58][59][60][61][62][63]. A few of these findings are discussed here.…”

Section: Thermo-mechanical Integrity and Reliabilitymentioning

confidence: 98%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

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Design and fabrication of a reliability test chip for 3D-TSV

Cited by 25 publications

References 23 publications

Resistance increase due to electromigration induced depletion under TSV

Resistance increase due to electromigration induced depletion under TSV

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

3D integration review

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