Detection of catastrophic faults in analog integrated circuits

Milor, Linda; Visvanathan, V.

doi:10.1109/43.21830

Cited by 199 publications

(81 citation statements)

References 16 publications

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“…For maximizing a 0 we have the objective function as given by (10), subject to constraints (11) through (15). Note that here we have set out to find MSDF of R 1 .…”

Section: Problem Description and Sketch Of Solutionmentioning

confidence: 99%

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High sensitivity test signatures for unconventional analog circuit test paradigms

Sindia

Agrawal

2013

2013 IEEE International Test Conference (ITC)

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Abstract-A method of testing for parametric faults in analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the root mean square (RMS) magnitude of the applied input voltage at a relevant frequency or DC. The test then classifies the CUT as fault-free or faulty based upon a comparison of the estimated polynomial coefficients with those of the fault-free circuit. The test application needs very little augmentation of the circuit to make it testable as only output parameters are used for classification. The method is validated on an active elliptic filter and is shown to uncover parametric faults causing deviations as small as 5% from nominal values. Fault diagnosis based upon sensitivity of polynomial coefficients at relevant frequencies is discussed. Another type of circuit signatures in the form of probability moments of the output when test input is random noise are also proposed. It is shown that the sensitivity of either signature can be enhanced by a newly proposed nonlinear Vtransform. Finally, an adaptive test framework leveraging from these signatures and the transform technique is shown to improve defect level and yield loss.

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“…For maximizing a 0 we have the objective function as given by (10), subject to constraints (11) through (15). Note that here we have set out to find MSDF of R 1 .…”

Section: Problem Description and Sketch Of Solutionmentioning

confidence: 99%

“…Testing of linear circuits is well studied and several methods can be found in the literature [9], [15]- [17]. Guo and Savir [9] describe a scheme that is representative of coefficient based test schemes for analog circuits.…”

Section: Introductionmentioning

confidence: 99%

High sensitivity test signatures for unconventional analog circuit test paradigms

Sindia

Agrawal

2013

2013 IEEE International Test Conference (ITC)

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“…The 100 patterns for the CUT discrete elements parameters dispersed randomly in their tolerance regions δ DEV = ± 5% (set I) and for eight Table 4 CUT performance parameters estimation errors and their standard deviations assumed special cases with the one selected element value shifted from the nominal point and randomly determined other ones (set II) were tested during this experiment. The filter circuit performance parameters were calculated basing on the regression models found evolutionarily (22)(23)(24)(25)(26)(27)(28)(29)(30)(31). Finally, identically as in [31], the CUT pattern is classified into the good ones if all the tested performance parameters do not exceed the allowed tolerance absolute deviation ± | p i | from the nominal level specified and to the faulty ones otherwise ( Table 5).…”

Section: Examples Of Low-pass Filters Testingmentioning

confidence: 99%

“…Generally, analog electronic circuit testing concepts may be classified into fault-driven and specification-driven groups [22,23]. The first class consists of approaches which are dedicated to faulty elements detections and optionally their locations and identifications.…”

Section: Introductionmentioning

confidence: 99%

Analog Circuit Specification Testing by Means of Walsh–Hadamard Transform and Multiple Regression Supported by Evolutionary Computations

Golonek

Machniewski

2017

Circuits Syst Signal Process

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This paper describes an approach for an analog electronic circuit specification quick verification that is based on a simple mathematical model determined during the before-test stage statistical analysis. Generally, the observed performance parameters (e.g., cutoff frequency, phase shift at the assumed frequency point) are calculated from the Walsh-Hadamard transform components of circuit under test step time response. The optimal estimating formulas for relationship between the tested specifications and the selected components of the spectra are defined in the system based on a linear multiple regression procedure supported by genetic programming. The evolutionary computations significantly improve the approximation effectiveness by selecting the most representative points of the sequences domain and by defining the optimal set of linearizing functions. Finally, at the test stage, only a simple step stimulus and time-effective calculations are required to the tested performance parameters (specifications) of analog circuit identification and it predisposes the approach to quick production testing procedure realization or to embedding it in the mixed-signal systems. The automated built-in self-testing procedure using this concept may be easily implemented to low-cost microcontroller equipped with AD converter used for the testing response samples acquiring.

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“…Although many AC, DC and transient test generation techniques [1,2,3,4,5] have been proposed, most of these are restricted to small circuits mainly due to high simulation complexity and lack of realistic fault models which can handle large number of possible faults. Since complex analog circuits are typically built using well understood analog macro cells like opamps, comparators, current mirrors, multipliers, references, data converters, etc., the problem of testing large complex circuits can be reduced to hierarchical testing of these macro cells, as test generation techniques for testing these cells is available.…”

Section: Introductionmentioning

confidence: 99%

Robust optimization based backtrace method for analog circuits

Gomes

Chatterjee

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)

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In this paper, we propose a new robust approach to signal backtrace for efficiently testing embedded analog modules in a large system. The proposed signal backtrace method is formulated as a solution to a multi-point boundary value problem(BVP), with constraints on the output state and the input. This error constraint minimizes large spurious deviations in the input signal and the convergence problems that arise if multiple solutions exist or if the desired signal does not exist in the feasible signal space. As an additional attractive advantage, this formulation preserves the core iteration structure of a SPICE-like simulator without modifications, greatly easing implementation.

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Detection of catastrophic faults in analog integrated circuits

Cited by 199 publications

References 16 publications

High sensitivity test signatures for unconventional analog circuit test paradigms

High sensitivity test signatures for unconventional analog circuit test paradigms

Analog Circuit Specification Testing by Means of Walsh–Hadamard Transform and Multiple Regression Supported by Evolutionary Computations

Robust optimization based backtrace method for analog circuits

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