2013 IEEE International Test Conference (ITC) 2013
DOI: 10.1109/test.2013.6651884
|View full text |Cite
|
Sign up to set email alerts
|

High sensitivity test signatures for unconventional analog circuit test paradigms

Abstract: Abstract-A method of testing for parametric faults in analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the root mean square (RMS) magnitude of the applied input voltage at a relevant frequency or DC. The test then classifies the CUT as fault-free or faulty based upon a comparison of the estimated polynomial coefficients with those of the fault-free circuit. The test application n… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1

Citation Types

0
3
0

Year Published

2014
2014
2022
2022

Publication Types

Select...
2
1
1

Relationship

0
4

Authors

Journals

citations
Cited by 4 publications
(3 citation statements)
references
References 31 publications
0
3
0
Order By: Relevance
“…Signal Flow Graph (SFG) based approach was proposed by R. Ramadoss et al [1] for detection of parametric fault detection of linear analog circuit where SFGs are inverted, and reverse simulated with good and faulty outputs to obtain test waveforms and component tolerances. Sindia and Agrawal [6,7] proposed a method of testing for parametric faults in non-linear analog circuits based on a polynomial representation of fault-free function of the CUT, using Taylor series expansion. The response of the CUT is estimated as a polynomial in the root mean square (RMS) magnitude of the applied input voltage at a relevant frequency or DC.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…Signal Flow Graph (SFG) based approach was proposed by R. Ramadoss et al [1] for detection of parametric fault detection of linear analog circuit where SFGs are inverted, and reverse simulated with good and faulty outputs to obtain test waveforms and component tolerances. Sindia and Agrawal [6,7] proposed a method of testing for parametric faults in non-linear analog circuits based on a polynomial representation of fault-free function of the CUT, using Taylor series expansion. The response of the CUT is estimated as a polynomial in the root mean square (RMS) magnitude of the applied input voltage at a relevant frequency or DC.…”
Section: Introductionmentioning
confidence: 99%
“…In almost all literature reported so far till date, the fault detection algorithm for detection of parametric faults has been developed for single-input single-output analog circuits e.g., Sallenkey band pass lter [5,8], low pass lter [3,4,7,8], leapfrog lter [1,3,5] or Elliptic lter circuit [6,7] where, the Op-amp is con gured for single ended operation and the noninverting input is grounded. In this paper, an utmost effort paid off in parametric fault detection in analog circuits where Opamp is con gured for double ended operation.…”
Section: Introductionmentioning
confidence: 99%
“…Some generic approaches exist for providing an initial set of signatures, such as direct current (dc) probing, I DDQ test, V -transform coefficients [4], process monitoring [5], etc. Work has been also presented on optimizing a particular stimulus to define optimized signatures [1], [6].…”
Section: Alternate Test: Background and Open Problemsmentioning
confidence: 99%