Designing Morphology in Epitaxial Silicon Nanowires: The Role of Gold, Surface Chemistry, and Phosphorus Doping

Abstract

Vertically aligned semiconductor nanowires (NWs) have many potential applications for NW-based technologies, ranging from solar cells to intracellular sensors. Aligned NWs can be fabricated by top-down etching of planar wafers or synthesized from the bottom up using the vapor-liquid-solid (VLS) mechanism to induce epitaxial growth on lattice-matched substrates. The VLS process permits the modulation of dopants along the NW growth axis, which if combined with dopant-dependent wet-chemical etching, can be used to encode precise morphology. However, the synthesis of vertical and linear NWs with complex morphology is nontrivial, requiring control over multiple interdependent aspects of the VLS process. Here, we demonstrate sub-10 nm morphology in ⟨111⟩ epitaxial silicon (Si) NWs grown by the VLS mechanism on (111) Si substrates with gold (Au) catalysts. Using silane (SiH), phosphine (PH), and hydrochloric acid (HCl) precursor gases at 480 °C, precise morphology is encoded through abrupt phosphorus (P) dopant transitions, which are found to be less than 5 nm in width. The results highlight three mechanistic attributes of the process. First, NW growth in the ⟨111⟩ direction is found to be unstable at high SiH partial pressures and growth rates unless using HCl, which stabilizes NW growth through chlorination of the NW sidewall. Second, aggregated Au deposited on the NW surface by the VLS catalyst is found to be immobile on the chlorinated surface and to impede selective wet-chemical etching by potassium hydroxide (KOH) solution, preventing the design of precise morphology. Third, the aggregation of Au is found to be strongly dependent on the SiH partial pressure and NW growth rate, and values exceeding ∼100 mTorr and ∼150 nm/min, respectively, are required to minimize Au and thereby enable selective wet-chemical etching. Under optimized growth conditions, we find that abrupt, complex, and arbitrary dopant profiles and morphologies can be encoded in vertical Si NWs, and we expect that a variety of electronic and photonic applications can be realized with these designed nanostructures.

Alloy-assisted deposition of three-dimensional arrays of atomic gold catalyst for crystal growth studies

“…Even if Au atoms were deposited over the sidewall during the synthesis, they tended to quickly de-wet and form nanoparticle aggregates 11 . Finally, phosphorus, as decomposed from phosphine (PH 3 , an n -type dopant precursor), is known to interact strongly with both Si and Au 16 , 33 , 42 and preferentially accumulate around the nanowire surfaces in n -type Si nanowires 43 . Indeed, previous results on n -type silicon spicules indicate minimum gold-based gradient along Si nanowire sidewalls 11 , confirming the immobilization role of phosphorus over Au.…”

The Geode Process I: Hollow Silica Microcapsules as a High Surface Area Substrate for Semiconductor Nanowire Growth

“…The bottom-up growth of semiconductor nanowires through the vapor-liquid-solid (VLS) mechanism offers exquisite control over nanowire structure and composition, 1-2 and thus functionality. [2][3][4][5][6] Demonstrations of prototype transistors, 7-10 photodetectors, [11][12][13] solar cells, [14][15][16][17] and biosensors [18][19][20][21] , for example, highlight the promise of these materials for electronic, photonic, energy conversion, and medical applications. However, it remains difficult to produce nanowires in large quantities, especially those with the nanoscale compositional complexity required for the above applications.…”

DREM2: a facile fabrication strategy for freestanding three dimensional silicon micro- and nanostructures by a modified Bosch etch process

“…Three dimensional (3D) silicon micro-and nanomachining has attracted a lot of interest in recent years for both research and industrial uses, and several promising applications have been proposed and demonstrated, e.g. vertically stacked silicon nanowires for field effect transistors (FET) [1], unified memory [2] and biosensors [3], shape-modified silicon nanopillars for quantum transport study [4] and FET [5], 3D silicon single cubic structures for 3D photonic crystal structures [6], etc. However, to easily fabricate 3D micro-and nanostructures, and simultaneously obtain a good size and shape control of the fabricated structures, is still considered to be difficult.…”

“…Bottom-up methods can create single crystalline silicon nanostructures, and the morphology can be encoded [6], however, this method is difficult to be integrated in traditional complementary metal-oxide-semiconductor (CMOS) industries. Top-down approaches, which can transfer the 2D lithography patterns into silicon in a 3D structure have been studied extensively before, e.g.…”