Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter

Uyttenhove, K.; Vandenbussche, J.; Lauwers, E.; Gielen, Georges; Steyaert, Michiel

doi:10.1109/jssc.2002.808306

Cited by 35 publications

(11 citation statements)

References 17 publications

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“…Since A/Dc or D/Ac would consume so much power at the present technology [4], our wireless endoscopy capsule system could not contain A/Dc or D/Ac. The receiver inside the capsule must restore the original digital data in the analog field and the transmitter must implement the digital modulation in the analog field.…”

Section: Architecture Descriptionmentioning

confidence: 99%

A 2.4 GHz low power wireless transceiver analog front-end for endoscopy capsule system

Chi

Yao

Han

et al. 2007

Analog Integr Circ Sig Process

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This work presents the design and implementation of a 2.4 GHz low power wireless transceiver analog front-end for the endoscopy capsule system in 0.25 lm CMOS. The prototype integrates a low-IF receiver analog front-end (low noise amplifier, double-balanced downconverter, band-pass-filtered AGC loop, and ASK demodulator) and a direct-conversion transmitter analog front-end (20 MHz IF PLL with well-defined amplitude control circuit, ASK modulator, up-converter, and output buffer) on a single chip together with one integrated RF oscillator and two LO buffers. Trade-off has been made over the design boundaries of the different building blocks to optimize the overall system performance. All building blocks feature the circuit topologies that enable comfortable operation at low power consumption. As a result, the IC works at a 2.5 V power supply, while only consuming 15 mW in receiver (RX) mode and 14 mW in transmitter (TX) mode. To build a complete transceiver for the endoscopy capsule system, only an antenna, a duplexer, and a digital controller are needed besides the presented analog front-end chip.

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Section: Architecture Descriptionmentioning

confidence: 99%

A 2.4 GHz low power wireless transceiver analog front-end for endoscopy capsule system

Chi

Yao

Han

et al. 2007

Analog Integr Circ Sig Process

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“…CMOS folding and/or interpolating ADCs have been proved a suitable architecture for highspeed ADCs with moderate resolution [1][2][3]. Those with sample rate up to 300 M Sample/s are described in [4][5][6]. These designs, however, occupy an area of more than 1.2 mm 2 , which is not suitable for embedded applications.…”

Section: Introductionmentioning

confidence: 99%

An 8-bit 200-MSample/s Folding and Interpolating ADC in 0.25 mm2

Chen

Ren

2006

Analog Integr Circ Sig Process

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This article is presented to describe an area-efficient CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application, which is fully compatible with standard digital CMOS technology. A modified MOStransistor-only folding block contributes to a small chip area. At the input stage, offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio (SNDR). An INL/DNL of 0.77 LSB/0.6 LSB was measured. An SNDR figure of 43.7 dB is achieved at 4 MHz input frequencies when operated at full speed of 200 MHz. The chip is realized in a standard digital 0.18 µm CMOS technology and consumes a total power of 181 mW from 3.3 V power supply. The active area is 0.25 mm 2 .

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“…The main building blocks of comparators, such as flipflops and latches, have been well analyzed, and include: a formula describing the occurrence probability of metastable states [2]; formulae for sensitivity [3]; theoretical analysis based on small signal devices [4], [5]; and design optimizations of high-speed comparators [5]- [7] have been reported. Moreover, there have been many reports on high-speed analog/digital converters (ADC) or comparators that discuss the effect of the static offset voltage, the metastability, the latch reset time [8]- [13], and the preamp frequency response [7], [10]. The frequency response model of comparators has not, however, been reported.…”

Section: Introductionmentioning

confidence: 99%

Frequency Response Analysis of Latch Utilized in High-Speed Comparator

Okura

Ohkura

Taniguchi

et al. 2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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We investigated the dynamic nature of a highspeed CMOS comparator, and present a comparator frequencyresponse model based on small-signal linear analysis of a latch. The analytical frequency model offers good insight into the linearity of the quantizer utilized in CT∆Σ modulators. In addition, a novel design guideline for a high-speed CMOS comparator to ensure the quantizer linearity is presented.

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Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter

Cited by 35 publications

References 17 publications

A 2.4 GHz low power wireless transceiver analog front-end for endoscopy capsule system

A 2.4 GHz low power wireless transceiver analog front-end for endoscopy capsule system

An 8-bit 200-MSample/s Folding and Interpolating ADC in 0.25 mm2

Frequency Response Analysis of Latch Utilized in High-Speed Comparator

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