Design study of the gate-all-around silicon nanosheet MOSFETs

Lee, Yong-Woo; Park, Geon-Hwi; Choi, Byoung Ho; Yoon, Jinsu; Kim, Hyojin; Kim, Dae Hwan; Kim, Dong Myong; Kang, Min-Ho; Choi, Sung-Jin

doi:10.1088/1361-6641/ab6bab

Cited by 32 publications

(10 citation statements)

References 23 publications

(27 reference statements)

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“…We have selected other published works on low-dimensional FETs to fairly assess the device performance of the proposed AlSi 3 FET. The selected published models include co-decorated SiNR FET [ 21 ], 27-ASiNR FET [ 20 ], Si nanowire (SiNW) FET [ 34 ], Si thin sheet FET [ 35 ], carbon nanotube (CNT) FET [ 36 ], graphene nanoribbon (GNR) FET [ 37 ], black phosphorene (BP) FET [ 38 ], and monolayer molybdenum disulfide (MoS 2 ) FET [ 39 ]. To concisely compare the device performance metrics, the comparisons are presented as bar graphs as shown in Fig 6 .…”

Section: Performances Analysis and Discussionmentioning

confidence: 99%

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

et al. 2022

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Moore’s Law is approaching its end as transistors are scaled down to tens or few atoms per device, researchers are actively seeking for alternative approaches to leverage more-than-Moore nanoelectronics. Substituting the channel material of a field-effect transistors (FET) with silicene is foreseen as a viable approach for future transistor applications. In this study, we proposed a SPICE-compatible model for p-type (Aluminium) uniformly doped silicene FET for digital switching applications. The performance of the proposed device is benchmarked with various low-dimensional FETs in terms of their on-to-off current ratio, subthreshold swing and drain-induced barrier lowering. The results show that the proposed p-type silicene FET is comparable to most of the selected low-dimensional FET models. With its decent performance, the proposed SPICE-compatible model should be extended to the circuit-level simulation and beyond in future work.

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Section: Performances Analysis and Discussionmentioning

confidence: 99%

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

et al. 2022

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“…Recently, silicon nanosheet devices have attracted a significant increase in interest, both for use in integrated nanoscale electronics and for studying fundamental properties in small scales [ 1 , 2 , 3 , 4 ]. In order to achieve reliable devices or test structures at nanoscale dimensions, it is necessary to control doping levels on silicon nanosheets and to reduce leakage power.…”

Section: Introductionmentioning

confidence: 99%

Modeling and Simulation Investigation of Ferroelectric-Based Electrostatic Doping for Tunnelling Field-Effect Transistor

et al. 2023

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In this paper, a novel ferroelectric-based electrostatic doping (Fe-ED) nanosheet tunneling field-effect transistor (TFET) is proposed and analyzed using technology computer-aided design (TCAD) Sentaurus simulation software. By inserting a ferroelectric film into the polarity gate, the electrons and holes are induced in an intrinsic silicon film to create the p-source and the n-drain regions, respectively. Device performance is largely independent of the chemical doping profile, potentially freeing it from issues related to abrupt junctions, dopant variability, and solid solubility. An improved ON-state current and ION/IOFF ratio have been demonstrated in a 3D-calibrated simulation, and the Fe-ED NSTFET’s on-state current has increased significantly. According to our study, Fe-ED can be used in versatile reconfigurable nanoscale transistors as well as highly integrated circuits as an effective doping strategy.

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“…Thanks to these structural changes and the success of FinFET through process optimization, the introduction of a gate-all-around (GAA) structure has recently been actively attempted in academia and industry. Among them, the nanosheet structure is in the spotlight as a strong candidate because it has gate controllability for channels superior to FinFET and more immunity for short channels [5][6][7]. It is expected that scaling due to such a structural change will have a limitation of less than or equal to 3 nm technology node, and a new channel material is attracting attention.…”

Section: Introductionmentioning

confidence: 99%

Device and Circuit Analysis of Double Gate Field Effect Transistor with Mono-Layer WS2-Channel at Sub-2 nm Technology Node

Park

Lim

et al. 2022

Nanomaterials

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In this work, WS2 was adopted as a channel material among transition metal dichalcogenides (TMD) materials that have recently been in the spotlight, and the circuit power performance (power consumption, operating frequency) of the monolayer WS2 field-effect transistor with a double gate structure (DG WS2-FET) was analyzed. It was confirmed that the effective capacitance, which is circuit power performance, was greatly changed by the extrinsic capacitance components of DG WS2-FET, and the spacer region length (LSPC) and dielectric constant (KSPC) values of the spacer that could affect the extrinsic capacitance components were analyzed to identify the circuit power performance. As a result, when LSPC is increased by 1.5 nm with the typical spacer material (KSPC = 7.5), increased operating speed (+4.9%) and reduced active power (–6.8%) are expected. In addition, it is expected that the spacer material improvement by developing the low-k spacer from KSPC = 7.5 to KSPC = 2 at typical LSPC = 8 nm can increase the operating speed by 36.8% while maintaining similar active power consumption. Considering back-end-of-line (BEOL), the change in circuit power performance according to wire length was also analyzed. From these results, it can be seen that reducing the capacitance components of the extrinsic region is very important for improving the circuit power performance of the DG WS2-FET.

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Design study of the gate-all-around silicon nanosheet MOSFETs

Cited by 32 publications

References 23 publications

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

Modeling and Simulation Investigation of Ferroelectric-Based Electrostatic Doping for Tunnelling Field-Effect Transistor

Device and Circuit Analysis of Double Gate Field Effect Transistor with Mono-Layer WS2-Channel at Sub-2 nm Technology Node

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