Design Space of Flexible Multigigabit LDPC Decoders

Abstract

Multigigabit LDPC decoders are demanded by standards like IEEE 802.15.3c and IEEE 802.11ad. To achieve the high throughput while supporting the needed flexibility, sophisticated architectures are mandatory. This paper comprehensively presents the design space for flexible multigigabit LDPC applications for the first time. The influence of various design parameters on the hardware is investigated in depth. Two new decoder architectures in a 65 nm CMOS technology are presented to further explore the design space. In the past, the memory domination was the bottleneck for throughputs of up to 1 Gbit/s. Our systematic investigation of column-versus row-based partially parallel decoders shows that this is no more a bottleneck for multigigabit architectures. The evolutionary progress in flexible multigigabit LDPC decoder design is highlighted in an extensive comparison of state-of-the-art decoders. Slot 0Slot 1

Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations

“…In a fully-parallel decoder architecture [8], each CN and VN is implemented by a separate hardware NPU. However, fullyparallel decoders are rarely practical due to the overwhelming routing complexity of the random interconnections between the nodes, and because they support only a single PCM, giving no flexibility over the block length or coding rate [9].…”

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

“…In the relatively less explored area of FPGA-based implementation, impressive results have recently been presented in works such as [15][16][17]. However, these are based on fully-parallel architectures which lack flexibility (code-specific) and are limited to small block sizes (primarily due to the inhibiting routing congestion) as discussed in the informative overview in [18]. Since our case study is based on fully automated generation of the hardware description language (HDL), we compare our results with some recent HLS-based stateof-the-art implementations [19][20][21][22] in Section 6.…”

High Speed Low Error Floor Hardware Implementation and Fast and Accurate Error Floor Estimation of LDPC Decoders

“…This is either as an initial step to application-specific integrated circuit (ASIC) implementation, or as a substitute for the much slower software simulations particularly for applications, such as optical communications and storage devices, where low error rates need to be reached. ASIC implementations result in faster and larger decoders, and there are also many high-throughput ASIC designs in the literature [24][25][26][27][28][29][30][31][32]. Structured LDPC codes such as Protograph-based LDPC codes [33] and Reed-Solomon-based LDPC codes (RS-LDPC) [34] are suitable for hardware implementation and have been widely used in almost all high-throughput LDPC decoders.…”

“…Protograph-based LDPC codes [33] have been shown to have excellent performance both in waterfall and error floor regions [3,35,36], while having a simple encoder and decoder structure [17,20,23,28,31,32,35,[37][38][39][40]. In particular, if the permutation matrices that produce the parity-check matrix of the lifted code from that of the base code are cyclic, the resulted (lifted) code is quasi-cyclic (QC).…”

“…In row-layered message-passing schedule, also known as layered message-passing or Turbo-Decoding Message-Passing (TDMP) [28,31,43], check nodes (rows of the parity check matrix) are processed in layers. Before the next layer of check nodes starts processing, variable nodes are updated with messages from current group of check nodes, and subsequently they create a new set of messages for the next group of check nodes.…”