DOI: 10.22215/etd/2014-10497
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High Speed Low Error Floor Hardware Implementation and Fast and Accurate Error Floor Estimation of LDPC Decoders

Abstract: This thesis explores hardware implementation of low error floor and high speed low-density parity-check (LDPC) decoders. At first, a novel partially-parallel implementation of a protograph-based quasi-cyclic (QC) LDPC decoder, using a new column-layered message-passing schedule is presented. A new design for serial-input check nodes and switch networks, results in lower hardware complexity while having a higher throughput and comparable latency in comparison with all existing partially-First, I would like to t… Show more

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Cited by 3 publications
(2 citation statements)
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“…for each variable node v ∈ V do 5: are connected to only one satisfied check node [23], [1], [16], [19], [32], [9]. This is particularly the case for irregular codes with degree-2 variable nodes [16], [19].…”
mentioning
confidence: 99%
“…for each variable node v ∈ V do 5: are connected to only one satisfied check node [23], [1], [16], [19], [32], [9]. This is particularly the case for irregular codes with degree-2 variable nodes [16], [19].…”
mentioning
confidence: 99%
“…Leafless ETSs (LETSs) are known to be the main problematic structures in the error floor region of variable-regular LDPC codes. For irregular LDPC codes, however, in addition to LETSs, there are other ETSs that are problematic but are not leafless, i.e., they have variable nodes that are connected to only one satisfied check node [62], [1], [47], [53], [76], [23]. This is particularly the case for irregular codes with degree-2 variable nodes [47], [53].…”
Section: Trapping Sets For Irregular Ldpc Codesmentioning
confidence: 99%