Design space exploration using time and resource duality with the ant colony optimization

Wang, Gang; Gong, Wenrui; DeRenzi, Brian; Kastner, Ryan

doi:10.1145/1146909.1147028

Cited by 18 publications

(5 citation statements)

References 16 publications

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“…have been widely reported in the literature for various applications to find the trade-off solutions to achieve the best possible compromise among multiple objectives. Among evolutionary algorithms, the genetic algorithm [30] and ant-colony optimization [31] have been employed for DSE for multicore architecture. Palesi et al [30] considered configuration space exploration for a SoC and extended the Platune tuning approach [32] using a genetic algorithm and exhaustive search to increase the exploration speed with many configurable parameters (e.g., voltage, capacitance).…”

Section: Related Workmentioning

confidence: 99%

“…Palesi et al [30] considered configuration space exploration for a SoC and extended the Platune tuning approach [32] using a genetic algorithm and exhaustive search to increase the exploration speed with many configurable parameters (e.g., voltage, capacitance). Wang et al [31] used ant-colony optimization for design space exploration to minimize the completion time of the applications while effectively utilizing the computational resources. This method finds a trade-off between hardware cost and timing performance.…”

Section: Related Workmentioning

confidence: 99%

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Estimation of distribution-based multiobjective design space exploration for energy and throughput-optimized MPSoCs

Murad¹,

Hussain²,

Ahmad³

et al. 2020

Turk J Elec Eng & Comp Sci

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Modern multicore architectures comprise a large set of components and parameters that require being matched to achieve the best balance between power consumption and throughput performance for a particular application domain.The exploration of design space for finding the best power-throughput trade-off is a combinatorial optimization problem with a large number of combinations, and. in general, its solution is prohibitively difficult to be explored exhaustively.However, fortunately, evolutionary algorithms (EAs) have the potential to efficiently solve this problem with reasonable computational complexity. In this paper, we consider a multiobjective design space exploration (DSE) problem with two conflicting objectives. The first objective corresponds to power consumption minimization while the second objective relates to throughput maximization. We approach this problem by employing the estimation of distribution algorithm (EDA), which belongs to the family of EAs. The proposed EDA-based DSE (EDA-DSE) scheme efficiently selects the design parameters (i.e. cache size, number of cores, and operating frequency) with an efficient power-throughput ratio.The proposed scheme is verified using cycle-accurate simulations over a set of benchmarks and the simulation results show a significant reduction in energy-delay product for all benchmark applications when compared to the default baseline configuration and genetic algorithm.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Estimation of distribution-based multiobjective design space exploration for energy and throughput-optimized MPSoCs

Murad¹,

Hussain²,

Ahmad³

et al. 2020

Turk J Elec Eng & Comp Sci

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show abstract

“…is family of algorithms did not appear in this domain until 2006, when [127,128] implemented an ACO to perform scheduling and allocation taking into account the objective functions delay and area. A comparison between Particle Swarm Optimization (PSO) and the evolutionary algorithms NSGA-II and WSGA was made in [11].…”

Section: Swarm Intelligence Systemsmentioning

confidence: 99%

Development of Multiobjective High-Level Synthesis for FPGAs

Bulnes

Maldonado

Trujillo

2020

Scientific Programming

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Traditionally, the High-Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) devices is a methodology that transforms a behavioral description, as the timing-independent specification, to an abstraction level that is synthesizable, like the Register Transfer Level. This process can be performed under a framework that is known as Design Space Exploration (DSE), which helps to determine the best design by addressing scheduling, allocation, and binding problems, all three of which are NP-hard problems. In this manner, and due to the increased complexity of modern digital circuit designs and concerns regarding the capacity of the FPGAs, designers are proposing novel HLS techniques capable of performing automatic optimization. HLS has several conflicting metrics or objective functions, such as delay, area, power, wire length, digital noise, reliability, and security. For this reason, it is suitable to apply Multiobjective Optimization Algorithms (MOAs), which can handle the different trade-offs among the objective functions. During the last two decades, several MOAs have been applied to solve this problem. This paper introduces a comprehensive analysis of different MOAs that are suitable to perform HLS for FPGA devices. We highlight significant aspects of MOAs, namely, optimization methods, intermediate structures where the optimizations are performed, HLS techniques that are addressed, and benchmarks and performance assessments employed for experimentation. In addition, we show the analysis of how multiple objectives are optimized currently in the algorithms and which are the objective functions that are optimized. Finally, we provide insights and suggestions to contribute to the solution of major research challenges in this area.

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“…Mouhoub and Hammami [28] make use of Multi Objective Evolutionary Algorithms (MOEA) to optimize FPGA architecture designs for on-chip memory usage, number of slices consumed, and execution time. Wang et al [39,40] propose a design space exploration methodology for optimal scheduling and architecture derivation based on ant colony optimization. They report a 17.3% improvement in performance over traditional force-directed scheduling.…”

Section: Architecture Exploration and Mappingmentioning

confidence: 99%

DesertFD: a finite-domain constraint based tool for design space exploration

Eames

Neema

Saraswat

2009

Des Autom Embed Syst

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As the complexity of computer based systems increases, designers are faced with the task of balancing a variety of design choices and parameters against conflicting optimization criteria. Design space exploration seeks to automate or partially automate the process of evaluating tradeoff decisions at design time. DesertFD is a domain-independent design space exploration tool which facilitates the representation and pruning of a design space using constraint satisfaction. DesertFD offers a formal tree-based view of a family of systems related through common structure, together with a flexible scripting language for modeling mathematical expressions governing property composition. User-specified constraints applied to the design space representation result in a pruning of the space. We discuss the reduction of the design space, property composition formulas and constraints into a constraint satisfaction problem using finite domain constraints. We examine two example design space exploration problems to evaluate DesertFD: the generation of a high level custom computer architecture for supporting H.264-based motion estimation, and the reliabilitydriven mapping of tasks to distributed embedded control units in a steer-by-wire automotive application.

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Design space exploration using time and resource duality with the ant colony optimization

Cited by 18 publications

References 16 publications

Estimation of distribution-based multiobjective design space exploration for energy and throughput-optimized MPSoCs

Estimation of distribution-based multiobjective design space exploration for energy and throughput-optimized MPSoCs

Development of Multiobjective High-Level Synthesis for FPGAs

DesertFD: a finite-domain constraint based tool for design space exploration

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