Wireless sensor networks (WSN) are one of the most evolving technologies applicable in various fields where sensitive information is required. However, the constraints of limited resources and requirements for environmentdependent connectivity and life cycle have urged designers to seek more efficient WSN infrastructures. In this paper, we have discussed and compared the results of various single path protocols i.e. LEACH, PAGASIS and VGA. Performance analysis of energy efficient multipath routing protocols incorporating wireless interference has also been performed.
Modern multicore architectures comprise a large set of components and parameters that require being matched to achieve the best balance between power consumption and throughput performance for a particular application domain.The exploration of design space for finding the best power-throughput trade-off is a combinatorial optimization problem with a large number of combinations, and. in general, its solution is prohibitively difficult to be explored exhaustively.However, fortunately, evolutionary algorithms (EAs) have the potential to efficiently solve this problem with reasonable computational complexity. In this paper, we consider a multiobjective design space exploration (DSE) problem with two conflicting objectives. The first objective corresponds to power consumption minimization while the second objective relates to throughput maximization. We approach this problem by employing the estimation of distribution algorithm (EDA), which belongs to the family of EAs. The proposed EDA-based DSE (EDA-DSE) scheme efficiently selects the design parameters (i.e. cache size, number of cores, and operating frequency) with an efficient power-throughput ratio.The proposed scheme is verified using cycle-accurate simulations over a set of benchmarks and the simulation results show a significant reduction in energy-delay product for all benchmark applications when compared to the default baseline configuration and genetic algorithm.
The initiation to have a concept of shared memory in processors has built an opportunity for thread level parallelism. In various applications, synchronization or ordering tools are utilized to have an access to shared data. Traditionally, multithreaded programming models usually suggest a set of low-level primitives, such as locks, to guarantee mutual exclusion. Possession of one or more locks protects access to shared data. But, due to some flaws they become a suboptimal solution. The idea of transactional memory is in research presently as an alternative to locks. Among which, one way is hardware transactional memory. Atomicity is well supported by using transactions in hardware. In this chapter, we have focused on hardware transactional memories and the work done on them so far.
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