Design space exploration of low-power flip-flops in FinFET technology

Mahmoodi, Ehsan; Gholipour, Morteza

doi:10.1016/j.vlsi.2020.06.006

Cited by 15 publications

(5 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Complementary metal‐oxide‐semiconductor (CMOS) technology scaling has become the main key to continuous progress in the silicon‐based semiconductor industry over the past three decades. However, as the technology scaling enters beyond 32 nm regime, CMOS devices face many serious problems such as increased leakage currents, difficulty with an increase in ON ‐current, large parametric variations, low reliability, increase in manufacturing cost, etc 6–10 . So, there is a need to look for different potential alternatives to CMOS.…”

Section: Introductionmentioning

confidence: 99%

“…However, as the technology scaling enters beyond 32 nm regime, CMOS devices face many serious problems such as increased leakage currents, difficulty with an increase in ON-current, large parametric variations, low reliability, increase in manufacturing cost, etc. [6][7][8][9][10] So, there is a need to look for different potential alternatives to CMOS. It is found that carbon nanotube field-effect transistors (CNTFET) and graphene nanoribbon field-effect transistors (GNRFET) have a higher power of switch, curves with more ideal voltage, and better mobility, consequently, they can be favorable replacements for CMOS.…”

mentioning

confidence: 99%

See 1 more Smart Citation

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

Abbasian,

Orouji,

Taghipour Anvari

et al. 2023

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

SummaryInternet‐of‐Things (IoTs)‐based embedded systems require energy‐efficient designs for long‐term operation. To achieve energy‐efficient designs, multiple‐valued logic (MVL) circuits and graphene nanoribbon field‐effect transistors (GNRFETs) are used instead of binary logic circuits and complementary metal‐oxide‐semiconductor (CMOS), respectively. This paper presents a novel ultra‐low power and energy‐efficient ternary Half‐Adder (THA) circuit based on unary operators, two power supplies (dual‐VDD), VDD and VDD/2, and two ternary 3:1 multiplexers in 32 nm GNRFET technology. The superiority of the proposed design are improvements between 2.86% and 60% in transistor count, between 86.12% and 97.15% in power consumption, and between 58.14% and 98.39% in power‐delay‐product (PDP) compared to existing THA circuits. Moreover, the proposed THA circuit is also implemented with 32 nm carbon nanotube field‐effect transistors (CNTFETs). Simulation results indicate that the proposed GNRFET‐based THA circuit increases delay by 1.74 × and reduces power/PDP by 89.41%/81.63% compared to its CNTFET‐based counterpart.

show abstract

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

Abbasian,

Orouji,

Taghipour Anvari

et al. 2023

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

show abstract

“…FinFET Gate width represents “2nh” here n and h specifies number and height of fins respectively 11–14 . The number of fins maximized to have higher on‐current, which creates maximizes the gate control on the channel, which diminish the Short channel effects 15,16 . But in SG‐FinFET, delay occurs in both read write operation.…”

Section: Introductionmentioning

confidence: 99%

“…[11][12][13][14] The number of fins maximized to have higher on-current, which creates maximizes the gate control on the channel, which diminish the Short channel effects. 15,16 But in SG-FinFET, delay occurs in both read write operation. Hence, leakage control transistor is used for the minimization of leakage power and delay.…”

mentioning

confidence: 99%

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

Sankranti,

Roji Marjorie

2023

Softw Pract Exp

View full text Add to dashboard Cite

Static random‐access memory (SRAM) plays a vital component of digital systems. The main issue of SRAM cells is power leakage, which results in an increase in chip area. Therefore this manuscript proposes a shorted‐gate fin‐type field‐effect transistor based SRAM cell utilizing leakage control transistor technique (SGFinFETs‐SRAM‐LECTOR) for decreasing the leakage power delay by improving the static noise margins (SNMs) together with power delay product (PDP). Here, the SGFinFETs‐SRAM‐LECTOR is primarily applied to stacking enhancement for lessening the leakage power dissipation (LPD). Two more transistors are used in LECTOR for reducing the leakage current with delay, which is based on transistor stacking. LECTOR employs two more transistors that are connected in series between pull‐up and pull‐down networks that means additional SG FinFETs PMOS transistor insertions amongst the pull‐up network and output terminal, additional SG FinFETs NMOS transistor insertions amidst the pull down network and output terminal. These additional transistors can decrease the leakage current. The simulation of the proposed approach is implemented in HSPICE simulation tool. Some metrics are computed to validate the efficacy of the proposed approach. Finally, the proposed technique reaches 11.31%, 51.47%, 45.46% less read delay, 44.44%, 26.33%, 33.45% less write delay, 36.12%, 45.28%, 26.45% less read power, 34.5%, 33.56%, 22.41% less write power, 37.4%, 15.3%, 26.54% high read SNM, 33.67%, 35.8%,12.09% high write SNM when analyzed to the existing models.

show abstract

“…For this reason, various HSPICE simulations at 7-nm predictive technology model multi-gate (PTM-MG) technology (P. T. M. (PTM)) has been done at LEVEL = 72, 25 ˚C temperature, and a certain range of supply voltage of V DD from 0.2 V to 0.5 V by a linear variation of 0.1 V. The effective width (W) of a FinFET is given in Eq. (1) as follows(Mahmoodi, 2020):…”

mentioning

confidence: 99%

A Comprehensive Analysis of Different SRAM Cell Topologies in 7-nm FinFET Technology

Abbasian

Birla

Gholipour

2021

Preprint

Self Cite

View full text Add to dashboard Cite

This article aims to provide a wide comparative analysis of different SRAM cells in 7nm FinFET Technology. Due to various limitations of the CMOS device in nanotechnology, FinFET is one of the trending choices for memory designers which can improve the stability and minimize the Short Channel Effects of the CMOS. Here, performance metrics of these SRAM cells like the stability, access time, power have been measured at a supply voltage range of 0.2 V to 0.5 V. The layout of the existing cells has been designed and compared in which the ST12T consumes the maximum area. The simulated results inferred that the ST11T SRAM cell offers the highest RSNM and the minimum dynamic and leakage power amongst all the SRAM cells. Moreover, ST12T SRAM cell has the highest WSNM in comparison to other SRAM cells. An electrical quality metric has been utilized, which displays the superiority of the ST12T SRAM cell amongst all the considered SRAM cells in this article.

show abstract

Design space exploration of low-power flip-flops in FinFET technology

Cited by 15 publications

References 16 publications

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

A Comprehensive Analysis of Different SRAM Cell Topologies in 7-nm FinFET Technology

Contact Info

Product

Resources

About