Design Space Exploration and System Optimization with SymTA/S &amp;#8212; Symbolic Timing Analysis for Systems

Hamann, Arne; Jersak, Marek; Richter, Kai; Ernst, Rolf

doi:10.1109/real.2004.17

Cited by 41 publications

(26 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These alternative approaches advocate the use of traffic shapers in order to obtain tight bounds on end-to-end behaviour [12,17]. However, the presented approach, which is completely data-driven, obtains higher throughput and lower latency, while still being amenable to performance analysis.…”

Section: Discussionmentioning

confidence: 99%

Monotonicity and run-time scheduling

Wiggers

Bekooij

Smit

2009

Proceedings of the Seventh ACM International Conference on Embedded Software

View full text Add to dashboard Cite

Modern embedded multi-processors can execute several streamprocessing applications concurrently. Typically, these applications are partitioned into tasks that communicate over buffers together forming a task graph. The fact that these applications are started and stopped by the user combined with the knowledge that not all applications are necessarily completely characterised makes it attractive to use run-time scheduling. We define and characterise a class of budget schedulers that by construction bound the interference from other applications. Furthermore, we will show that the worst-case effects of these schedulers can be included in dataflow process networks. The execution of the resulting dataflow process network is shown to result in tight and conservative bounds on the end-to-end temporal behaviour of the execution of the task graph on a cycle-true simulator. Given that the inter-task synchronisation of the application allows for a dataflow model that is functionally deterministic, this enables exploration of various buffer capacities and scheduler settings at a high level of abstraction.

show abstract

Section: Discussionmentioning

confidence: 99%

Monotonicity and run-time scheduling

Wiggers

Bekooij

Smit

2009

Proceedings of the Seventh ACM International Conference on Embedded Software

View full text Add to dashboard Cite

show abstract

“…Further work should also be done towards providing more directed feedback to a system designer, compared to what we have presented in this paper. Lastly, there are a number of recently developed tools for timing/schedulability analysis of embedded systems (see for example, [Amnell et al 2003;Hamann et al 2004]). It would certainly be meaningful to explore if our analysis can be incorporated inside these tools in a smooth way.…”

Section: Discussionmentioning

confidence: 99%

Interactive schedulability analysis

Bordoloi

Chakraborty

2007

ACM Trans. Embed. Comput. Syst.

View full text Add to dashboard Cite

A typical design process for real-time embedded systems involves choosing the values of certain system parameters and performing a schedulability analysis to determine whether all deadline constraints can be satisfied. If such an analysis returns a negative answer, then some of the parameters are modified and the analysis is invoked once again. This iteration is repeated till a schedulable design is obtained. However, the schedulability analysis problem for most task models is intractable (usually co-NP hard) and hence such an iterative design process is often very expensive. To get around this problem, we introduce the concept of "interactive" schedulability analysis. It is based on the observation that if only a small number of system parameters are changed, then it is not necessary to rerun the full schedulability analysis algorithm, thereby making the iterative design process considerably faster. We refer to this analysis as being "interactive" because it is supposed to be run in an interactive mode. This concept is fairly general and can be applied to a wide variety of task models. In this paper we have chosen the recurring real-time task model because it can be used to represent realistic applications from the embedded systems domain (containing conditional branches and fine-grained deadline constraints). Our experimental results show that using our scheme can lead to more than 20× speedup for each invocation of the schedulability analysis algorithm, compared to the case where the full algorithm is run.

show abstract

“…To the best of our knowledge, no other analysis technique/tool, except maybe the hybrid method of [11], is currently able to do a performance analysis for this type of systems (involving a dynamic memory bus and uncertain arrival times). Existing techniques for WCET analysis of distributed embedded systems, such as Modular Performance Analysis [12,13], SymTA/S [14] and MAST [15] are not applicable since they lead to overly conservative analysis results. In [11], a hybrid method is proposed for analyzing embedded real-time systems that integrates modular performance analysis and timed automata.…”

Section: Introductionmentioning

confidence: 99%

Verification of Printer Datapaths Using Timed Automata

Igna

Vaandrager

2010

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. In multiprocessor systems with many data-intensive tasks, a bus may be among the most critical resources. Typically, allocation of bandwidth to one (high-priority) task may lead to a reduction of the bandwidth of other tasks, and thereby eectively slow down these tasks. WCET analysis for these types of systems is a major research challenge. In this paper, we show how the dynamic behavior of a memory bus and a USB in a realistic printer application can be faithfully modeled using timed automata. We analyze, using Uppaal, the worst case latency of scan jobs with uncertain arrival times in a setting where the printer is concurrently processing an innite stream of print jobs.

show abstract

Design Space Exploration and System Optimization with SymTA/S — Symbolic Timing Analysis for Systems

Cited by 41 publications

References 16 publications

Monotonicity and run-time scheduling

Monotonicity and run-time scheduling

Interactive schedulability analysis

Verification of Printer Datapaths Using Timed Automata

Contact Info

Product

Resources

About