Design, processing and characterization of delta-doped channel AlGaAs/InGaAs/GaAs HFETs

Abstract

We report on design, processing and characterization of AlGaAs/InGaAs/GaAs HFETs which feature the power capabilities of double delta-doped devices and the low noise performance of the standard HFETs. To study the influence of delta doping position on the subband energies and sheet charge density, numerical simulations based on a self-consistent solution of Poisson's and Schrödinger's equations have been used for different channel thicknesses. Three different devices with a single δ-doped layer located at three different positions inside the channel have been fabricated and tested. On-wafer noise measurements have revealed that the position of the delta-doped layer can be optimized to minimize the noise figure without any relevant degradation of the maximum transconductance. The device with the delta-doped layer closer to the bottom heterointerface was found to exhibit the best performance in terms of the maximum cutoff and maximum oscillation frequencies and the minimum noise figure.

High-performance Ge/GaAs heterojunction tunneling FET with a channel engineering for sub-0.5 V operation

“…However, it is necessary to lower the supply voltage in order to reduce power consumption and the ambipolar current characteristics, which causes a dilemma in managing the operation condition. Various compound semiconductors have been introduced as base materials for electronic devices, owing to their high carrier mobility and switching speed [5][6][7][8][9][10]. Also, compound semiconductorsbased heterojunctions have been adopted in TFETs to enhance the current drivability, along with the geometrical design approaches [11,12].…”

Simulation for silicon-compatible InGaAs-based junctionless field-effect transistor using InP buffer layer

“…In this work, an InGaAs/InP junctionless (JL) metal-oxide-semiconductor field-effect transistor (MOSFET) with higher performances and fewer process and physical issues is extensively studied [16][17][18][19][20][21][22][23][24][25]. Device design and characterization was carried out by a most recent version of Silvaco ATLAS where virtual environments for state-of-the-art semiconductor device simulations are provided [26][27][28][29]. Since the current conduction in JL field-effect transistors (JLFET) is dominated by body (bulk) current, the quality of InGaAs layer is highly important.…”

Reduction of skin effect losses in double-level-T-gate structure

“…During the last three decades, the fabrication and performance of transistors operating in the GHz frequency range have been showing a rapid progress by introducing new material systems (e.g., GaAs/InGaAs 1-4 or AlGaN/GaN heterostructures [5][6][7] ), novel technological processes, [6][7][8][9] or new device geometries with decreasing gate dimensions. [10][11][12] The transistor scaling process has the drawback that the parasitic gate resistance increases linearly with decreasing gate length L g .…”