Simulation for silicon-compatible InGaAs-based junctionless field-effect transistor using InP buffer layer

Abstract

In this paper, we present the optimized performances of indium gallium arsenide (InGaAs)-based compound junctionless field-effect transistors (JLFETs) using an indium phosphide (InP) buffer layer. The proposed InGaAs-InP material combination with little lattice mismatch provides a significant improvement in current drivability securing various potential applications. Device optimization is performed in terms of primary dc parameters and characterization is investigated by two-dimensional (2D) technology computer-aided design simulations. The optimization variables were the channel doping concentration (N ch ), the buffer doping concentration (N bf ), and the channel thickness (T ch ). For the optimally designed InGaAs JLFET, on-state current (I on ) of 325 μA μm −1 , subthreshold swing (S) of 80 mV dec −1 , and current ratio (I on /I off ) of 10 9 were obtained. In the end, the results are compared with the data of silicon (Si)-based JL MOSFETs to confirm the improvements.

Impact of In_1-xGa_xAs Capping Layer on Characteristic of III-V Trigate MOSFET Devices

“…In summary, we have studied the impact of T cap and x of In 1x Ga x As capping layer on 14-nm In 1-x Ga x As / In 0.53 Ga 0.47 As / In 0.52 Al 0.48 As / InP trigate MOSFET. For the given specifications of SS < 72 mV/dec, the on-/off-state current ratio > 1.7×10 6 , DIBL < 55 mV/V with V th = 160 mV, the device with a 4-nm In 0.68 Ga 0.32 As capping layer may provide optimal characteristic for high-performance device applications. (c) Fig.…”

“…Recent studies on III-V FETs have shown fascinating characteristic from thin-channel planner MOSFETs [3][4]. III-V junctionless FET devices have also been reported for even superior on/off behavior and current ratio [5][6]. InGaAs/InAlAs is one of highly attractive III-V materials due to lattice match [7] and outstanding heterojunction transport property [8].…”

“…Notably, owing to similarity in materials of capping layer In 1-x Ga x As and channel layer In 0.53 Ga 0.47 As, the explored new device could be fabricated. By considering the shortchannel effect (SCE) parameters: I on /I off > 1.7×10 6 , subthreshold swing (SS) < 72 mV/dec, and drain induced barrier lowering (DIBL) < 55 mV/V simultaneously, we find the feasible range of T cap and x for high-performance device applications, where the threshold voltage (V th ) is targeted at 160 mV. Figure 1(a) illustrates a process flow for fabricating the explored III-V device.…”

High-performance Ge/GaAs heterojunction tunneling FET with a channel engineering for sub-0.5 V operation

“…However, it is necessary to lower the supply voltage in order to reduce power consumption and the ambipolar current characteristics, which causes a dilemma in managing the operation condition. Various compound semiconductors have been introduced as base materials for electronic devices, owing to their high carrier mobility and switching speed [5][6][7][8][9][10]. Also, compound semiconductorsbased heterojunctions have been adopted in TFETs to enhance the current drivability, along with the geometrical design approaches [11,12].…”

Simulation study of 14-nm-gate III-V trigate field effect transistor devices with In1−xGaxAs channel capping layer

“…2,3 III-V junctionless FET devices have also been reported for even superior on-/off-state current ratio. 4,5 InGaAs/InAlAs is one of highly attractive III-V materials due to little lattice mismatch 6 and outstanding heterojunction transport property. 7 III-V materials have the higher electron mobility than silicon one which can increase the driving current.…”