Design Procedure for Two-Stage CMOS Opamp using gm/ID design Methodology in 16 nm FinFET Technology

Hesham, Bakr; Hasaneen, El-Sayed; Hamed, Hesham F. A.

doi:10.1109/icm48031.2019.9021511

Cited by 6 publications

(1 citation statement)

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“…It explores the ratio between the small-signal transconductance (

) of a MOSFET and the DC drain current (

), known as the MOSFET efficiency. The

methodology has been widely used in analog integrated circuit designs to obtain very-low-power circuits for relatively low-frequency applications [ 4 , 6 , 15 , 16 , 17 , 18 , 19 ]. The main advantage of the methodology is that it provides a powerful sizing tool that allows the designer to take advantage of all the subthreshold regions to obtain very low power consumption circuits with very few iterations and significant time reduction in the design flow.…”

Section: Introductionmentioning

confidence: 99%

A gm/ID-Based Low-Power LNA for Ka-Band Applications

Galante-Sempere,

Torres-Clarke,

del Pino

et al. 2024

Sensors

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This article presents the design of a low-power low noise amplifier (LNA) implemented in 45 nm silicon-on-insulator (SOI) technology using the gm/ID methodology. The Ka-band LNA achieves a very low power consumption of only 1.98 mW andis the first time the gm/ID approach is applied at such a high frequency. The circuit is suitable for Ka-band applications with a central frequency of 28 GHz, as the circuit is intended to operate in the n257 frequency band defined by the 3GPP 5G new radio (NR) specification. The proposed cascode LNA uses the gm/ID methodology in an RF/MW scenario to exploit the advantages of moderate inversion region operation. The circuit occupies a total area of 1.23 mm2 excluding pads and draws 1.98 mW from a DC supply of 0.9 V. Post-layout simulation results reveal a total gain of 11.4 dB, a noise figure (NF) of 3.8 dB, and an input return loss (IRL) better than 12 dB. Compared to conventional circuits, this design obtains a remarkable figure of merit (FoM) as the LNA reports a gain and NF in line with other approaches with very low power consumption.

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“…It explores the ratio between the small-signal transconductance (

) of a MOSFET and the DC drain current (

), known as the MOSFET efficiency. The