Design-Oriented Study of Advanced Synchronous Reference Frame Phase-Locked Loops

Golestan, Saeed; Monfared, Mohammad; Freijedo, Francisco D.

doi:10.1109/tpel.2012.2204276

Cited by 355 publications

(207 citation statements)

References 39 publications

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“…Bu kuplajı ortadan kaldırmak için alt geçiren filtre kullanımı mümkün olmakla birlikte sistem dinamiğini arttırmak için kuplajı ortadan kaldıracak bir ara yüz kullanılması gerekmektedir [8][9][10][11][12][13].…”

Section: Faz Ki̇li̇tlemeli̇ çEvri̇m (Fkç)unclassified

“…Locked Loop (MRF-PLL)) SRE-FKÇ kullanımı ile dengeli şebeke gerilimi durumu söz konusu olduğunda faz kilitlenme başarıyla gerçekleşebilmektedir fakat dengesizlik oluştuğunda faz kilitlemeli çevrim çıkışında oluşan salınım dolayısıyla sistemin çalışmasında bozukluklar oluşabilmektedir [8]. Çoklu Referans Eksen Faz Kilitlemeli Çevrim (ÇRE-FKÇ) uygulamasında, pozitif ya da negatif yönde dönüşe bağlı olarak negatif ve pozitif bileşenlerden bağımsız hale gelebilmek için alt geçiren filtreler ve d/q ters dönüşüm matrisleri kullanılarak α/β eksenlerinde etkiler azaltılarak d/q dönüşümleri yapılmaktadır.…”

Section: çOklu Referans Eksen Faz Kilitlemeli çEvrim (çRe-fkç) (Multiunclassified

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ÇRE-FKÇ Yönteminin Sabit Noktalı İşaret İşleyicilerle Giriş Gerilimi Dengesizliği Olan Sistemlerde Kullanımı için Adaptasyonu

Özkılıç¹,

Obdan²

2018

Journal of Polytechnic

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Section: Faz Ki̇li̇tlemeli̇ çEvri̇m (Fkç)unclassified

Section: çOklu Referans Eksen Faz Kilitlemeli çEvrim (çRe-fkç) (Multiunclassified

ÇRE-FKÇ Yönteminin Sabit Noktalı İşaret İşleyicilerle Giriş Gerilimi Dengesizliği Olan Sistemlerde Kullanımı için Adaptasyonu

Özkılıç¹,

Obdan²

2018

Journal of Polytechnic

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“…However, the pre/in-loop filter has great influence on both the response speed and system stability. It has been pointed out in [24] that the open-loop bandwidth of PLL must be sufficiently lower than the minimum frequency of disturbances rejected by the filtering stage to avoid possible interactions between the filtering stage and the PLL loop. As a result, the settling time generally cannot be less than two fundamental grid cycles when considering distorted conditions.…”

Section: Introductionmentioning

confidence: 99%

A Novel Open-Loop Frequency Estimation Method for Single-Phase Grid Synchronization Under Distorted Conditions

Fang

Dong

et al. 2017

IEEE J. Emerg. Sel. Topics Power Electron.

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Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Abstract-In this paper, a new open-loop architecture with good dynamic performance and strong harmonic rejection capability is proposed for single-phase grid synchronization under distorted conditions. Different from previous single-phase grid synchronization algorithms based on the phase locked loop (PLL) technique, the proposed method is to estimate the frequency and phase angle of the grid voltage in an open-loop manner so that fast dynamic response and enhanced system stability can be achieved. Firstly, an open-loop frequency estimation algorithm is introduced under ideal grid condition. Then, it is extended to distorted grid voltages through the combination of the developed frequency estimation unit and a pre-filtering stage consisting of a second-order lowpass filter and a cascaded delayed signal cancellation (DSC) module. In addition, a transient process smoothing (TPS) unit is designed to achieve smooth frequency transients in cases where the grid voltage experiences fast and large changes. The working principle of the new frequency estimation algorithm and the developed single-phase grid synchronization approach is given in detail, together with some simulation and experiment results for verifying their performance.

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“…The used APF can produce phase error when the actual grid frequency is different from the cutoff frequency of the APF.As a result, the estimated phase angle from the SRF-PLL is distorted, including the second harmonic component. When the transformation matrix for synchronous frame PI current regulator with a distorted phase angle is used, synchronous dq-axis currents have specific ripple components [8]- [10]. The output phase current also includes harmonic components.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Phase Error Effects Due to Grid Frequency Variation of SRF-PLL Based on APF

Seong¹

2016

Journal of Power Electronics

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This paper proposes a compensation algorithm for reducing a specific ripple component on synchronous reference frame phase locked loop (SRF-PLL) in grid-tied single-phase inverters. In general, SRF-PLL, which is based on all-pass filter to generate virtual voltage, is widely used to estimate the grid phase angle in a single-phase system. In reality, the estimated grid phase angle might be distorted because the phase difference between actual and virtual voltages is not 90 degrees. That is, the phase error is caused by the difference between cut-off frequency of all-pass filter and grid frequency under grid frequency variation. Therefore, the effects on phase angle and output current attributed to the phase error are mathematically analyzed in this paper. In addition, the proportional resonant (PR) controller is adapted to reduce the effects of phase error. The validity of the proposed algorithm is verified through several simulations and experiments.

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Design-Oriented Study of Advanced Synchronous Reference Frame Phase-Locked Loops

Cited by 355 publications

References 39 publications

ÇRE-FKÇ Yönteminin Sabit Noktalı İşaret İşleyicilerle Giriş Gerilimi Dengesizliği Olan Sistemlerde Kullanımı için Adaptasyonu

ÇRE-FKÇ Yönteminin Sabit Noktalı İşaret İşleyicilerle Giriş Gerilimi Dengesizliği Olan Sistemlerde Kullanımı için Adaptasyonu

A Novel Open-Loop Frequency Estimation Method for Single-Phase Grid Synchronization Under Distorted Conditions

Analysis of Phase Error Effects Due to Grid Frequency Variation of SRF-PLL Based on APF

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