The phase locked-loops (PLLs) are probably the most widely used synchronization technique in grid-connected applications. The main challenge associated with the PLLs is how to precisely and fast estimate the phase and frequency when the grid voltage is unbalanced and/or distorted. To overcome this challenge, incorporating moving average filter(s) (MAF) into the PLL structure has been proposed in some recent literature. A MAF is a linear-phase finite impulse response filter which can act as an ideal low-pass filter, if certain conditions hold. The main aim of this paper is to present the control design guidelines for a typical MAF-based PLL. The paper starts with the general description of MAFs. The main challenge associated with using the MAFs is then explained, and its possible solutions are discussed. The paper then proceeds with a brief overview of the different MAF-based PLLs. In each case, the PLL block diagram description is shown, the advantages and limitations are briefly discussed, and the tuning approach (if available) is evaluated. The paper then presents two systematic methods to design the control parameters of a typical MAF-based PLL: one for the case of using a proportional-integral (PI) type loopfilter (LF) in the PLL, and the other for the case of using a proportional-integral-derivative (PID) type LF. Finally, the paper compares the performance of a well-tuned MAF-based PLL when using the PI-type LF with the results of using the PID-type LF, which provides useful insights into their capabilities and limitations.

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Abstract-Control of three-phase power converters in the synchronous reference frame is now a mature and well developed research topic. However, for single-phase converters, it is not as well-established as three-phase applications. This paper deals with the design of a synchronous reference frame multi-loop control strategy for single phase inverter-based islanded distributed generation (DG) systems. The proposed controller uses a synchronous reference frame PI (SRFPI) controller to regulate the instantaneous output voltage, a capacitor current shaping loop in the stationary reference frame to provide active damping and improve both transient and steady-state performances, a voltage decoupling feedforward to improve the system robustness, and a multi-resonant harmonic compensator to prevent low-order load current harmonics to distort the inverter output voltage. Since, the voltage loop works in the synchronous reference frame, it is not straightforward to fine-tune the control parameters and evaluate the stability of the whole closed loop system. To overcome this problem, the stationary reference frame equivalent of the voltage loop is derived. Then, a step-by-step systematic design procedure based on a frequency response approach is presented. Finally, the theoretical achievements are supported by experimental results.Index Terms-Single-phase inverter, stand-alone mode, multiloop, synchronous reference frame (SRF).

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To improve the performance of phase-locked loops (PLLs) under adverse grid conditions incorporating different filtering techniques into their structures have been proposed in literature. These filtering techniques can be broadly classified into in-loop and pre-loop filtering techniques depending on their position in the PLL structure. Inspired from the concept of delayed signal cancellation (DSC), the idea of cascaded DSC (CDSC) has recently been introduced as an effective solution to improve the performance of the PLL under adverse grid conditions. However, the focus has been on the application of CDSC operator as the pre-filtering stage of PLL, and little work has been conducted on its application as the in-loop filtering stage of PLL. This paper provides a detailed analysis and design of dqCDSC-PLL (PLL with in-loop dq-frame CDSC operator). The study is started with an overview of this PLL. A systematic design method to fine tune its control parameters is then proposed. The performance of the dqCDSC-PLL under different grid scenarios is then evaluated in details. It is then shown that how using the proportional-integral derivative controller as the loop filter can improve the response time of dqCDSC-PLL. A detailed comparison between the dqCDSC-PLL and moving average filter (MAF) based PLL (MAF-PLL) is then carried out. Through a detailed mathematical analysis, it is also shown that these PLLs are equivalent under certain conditions. The suggested guidelines in this paper make designing the dqCDSC-PLL a simple and straightforward procedure. Besides, the analyses performed in this paper provide a useful insight for designers about the advantages/disadvantages of dqCDSC-PLL for their specific applications.

One of the most important aspects for the proper operation of the single-phase grid-tied power-conditioning systems is the synchronization with the utility grid. Among various synchronization techniques, phase locked loop (PLL) based algorithms have found a lot of interest for the advantages they present. Typically, the single-phase PLLs use a sinusoidal multiplier as the phase detector (PD). These PLLs are generally referred to as the power-based PLL (pPLL). In this paper, the drawbacks associated with the pPLL technique (i.e., the sensitivity to the grid voltage variations, and the double frequency oscillations which appear in the estimated phase/frequency) are discussed in detail, and some of the previously reported solutions are examined. Then, to overcome these drawbacks, a simple and effective technique, called the double-frequency and amplitude compensation (DFAC) method is proposed. The effectiveness of the proposed method is evaluated through a detailed mathematical analysis. A systematic design method to finetune the PLL parameters is then suggested, which guarantees a fast transient response, a high disturbance rejection capability, and a robust performance. Finally, the simulation and experimental results are presented, which highlight the effectiveness of the proposed PLL.

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In this study, a simple digital power control technique for single-phase grid-tie converters is proposed. The suggested technique is based on the application of dead-beat control theory to the instantaneous powers in the virtual two-axis reference frame. A voltage estimation scheme is added to the proposed direct power control algorithm that allows grid voltage sensorless operation. The simulation and experimental results confirm that the proposed control strategy provides fast, accurate and decoupled power control with a lower alternating current distortion.