Design of VLSI CMOS circuits under thermal constraint

Daasch, W.R.; Lim, Chee How; Cai, George

doi:10.1109/tcsii.2002.806247

Cited by 21 publications

(17 citation statements)

References 6 publications

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“…LDL is unaffected by any dynamic scaling of the clock cycle [1][2][3]. An asynchronous input port (Fig.…”

Section: Locally Delayed Latchingmentioning

confidence: 99%

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Two-phase synchronization with sub-cycle latency

Dobkin¹,

Ginosar²

2009

Integration

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“…LDL is unaffected by any dynamic scaling of the clock cycle [1][2][3]. An asynchronous input port (Fig.…”

Section: Locally Delayed Latchingmentioning

confidence: 99%

“…Moreover, in order to reduce power consumption, frequency and voltage may also be changed dynamically in DVFS systems [1][2][3], leading to changing clock relations during chip operation.…”

Section: Introductionmentioning

confidence: 99%

Two-phase synchronization with sub-cycle latency

Dobkin¹,

Ginosar²

2009

Integration

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“…LDL is unaffected by clock cycle changes that can be caused for instance due to dynamic frequency or voltage scaling [2]- [4]. There is also no restriction on stopping the clock during periods of inactivity.…”

Section: A Ldl Principlesmentioning

confidence: 99%

High Rate Data Synchronization in GALS SoCs

Dobkin

Ginosar

Sotiriou

2006

IEEE Trans. VLSI Syst.

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Abstract-Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failures if the delay of their locally-generated clock tree is not considered. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the magnitude of clock tree delays, the cycle times of the GALS module, and the complexity of the asynchronous interface controllers using a timed signal transition graph (STG) approach. In some cases, the problem can be solved by extracting all the delays and verifying whether the system is susceptible to metastability. In other cases, when high data bandwidth is not required, matched-delay asynchronous ports may be employed. A novel architecture for synchronizing inter-modular communications in GALS, based on locally delayed latching (LDL), is described. LDL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates. It replaces complex global timing constraints with simpler localized ones. Three different LDL ports are presented. The risk of metastability in the synchronizer is analyzed in a technology-independent manner.

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“…A more general approach of optimization with thermal constraints described as partial differential equations is given in [11]. Other approaches for temperature control of systems and devices can be implemented using fuzzy controllers [12] or thermal compensation circuits [13], [14]. Pruhs and coauthors formulate the processor speed control problems with power, thermal, and task precedence constraints as scheduling optimization problems and present heuristic algorithms to solve them [15], [16].…”

Section: Introductionmentioning

confidence: 99%

Processor Speed Control With Thermal Constraints

Mutapcic

Boyd

Murali

et al. 2009

IEEE Trans. Circuits Syst. I

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Abstract-We consider the problem of adjusting speeds of multiple computer processors, sharing the same thermal environment, such as a chip or multichip package. We assume that the speed of each processor (and associated variables such as power supply voltage) can be controlled, and we model the dissipated power of a processor as a positive and strictly increasing convex function of the speed. We show that the problem of processor speed control subject to thermal constraints for the environment is a convex optimization problem. We present an efficient infeasible-start primal-dual interior-point method for solving the problem. We also present a distributed method, using dual decomposition. Both of these approaches can be interpreted as nonlinear static control laws, which adjust the processor speeds based on the measured temperatures in the system. We give numerical examples to illustrate performance of the algorithms.Index Terms-Convex optimization, distributed control, primal-dual interior-point methods, temperature-aware processor control.

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Design of VLSI CMOS circuits under thermal constraint

Cited by 21 publications

References 6 publications

Two-phase synchronization with sub-cycle latency

Two-phase synchronization with sub-cycle latency

High Rate Data Synchronization in GALS SoCs

Processor Speed Control With Thermal Constraints

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