Design of two-terminal-electrode vertical thyristor as cross-point memory cell without selector

Abstract

We proposed a two-terminal-electrode vertical thyristor and investigated its suitability as a cross-point memory cell without a selector from the viewpoints of p+- and n+-base region width and a vertically stacked doped-epitaxial-Si layer structure such as p++-emitter/n+-base/p+-base/n++-emitter or n++-emitter/p+-base/n+-base/p++-emitter. The proper p+- and n+-base-region width (i.e., 160 nm) and p++-emitter/n+-base/p+-base/n++-emitter layer structure could enable the development of a cross-point memory cell using the half bias concept by preventing misfit dislocations at the junctions between the n++-emitter and p+-base or n+-base and p++-emitter. It was also found that generation of the misfit dislocations originating from B or P atom segregation at junctions during doped-Si epitaxial-layer growth enhanced the strain at the junctions. The misfit dislocations at the junctions were produced when the strain at the junctions was greater than ∼4 × 10−4.

Highly Reliable Memory Operation of High Density Three-Terminal Thyristor Random Access Memory

“…2-T TRAM has the advantage of its simple structure that allows a cost-effective cross-point array fabrication with conventional Si processes. Yet, the drawbacks are the low data retention and array disturbance that stem from the weak controllability of the storage area [10][11][12]. On the other hand, a three-terminal (3-T) TRAM, whose gate bias controls the energy band of the storage region, can remedy these drawbacks; the proper adjustment of gate-cathode voltage (V GC ) can improve the retention characteristics and the array disturbance immunity by anode-cathode voltage (V AC ) [13][14][15][16].…”

“…Even though there have been many studies to improve the capacitor technologies, such as new high-k materials [5][6][7] and a high-aspect-ratio 3D capacitor structure [8,9], these approaches possess the issue of increasing fabrication complexities and high cost [2][3]. To overcome these challenges, a capacitorless 1T DRAM structure, namely a thyristor-based random-access memory (TRAM), has been proposed as an alternative in which the charge is stored at the internal p-base and n-base storage area [10][11][12][13][14][15][16]. The TRAM can operate as a two-terminal (2-T) device by modulating the energy band with only the anode and cathode biases [10][11][12].…”

Electrical and Data-Retention Characteristics of Two-Terminal Thyristor Random Access Memory

“…Various types of 1T DRAM such as floating body RAM (FB-RAM), zero ionization-zero swing FET (Z 2 -FET), and thyristor random access memory (TRAM) without the capacitor have been studied to overcome the fabrication complexities and the physical limits of the 1T-1C DRAM [7]- [18]. The two-terminal (2-T) TRAM can be one of the most promising 1T DRAM technologies for the nanoscale cross-point vertical array due to its high potential for aggressive device scaling and simple fabrication process [17]- [18]. The 2-T TRAM can modulate the energy band by using only the anode and cathode bias, which can provide an effective pathway to achieve a 4F 2 memory feature size and a 3-D stack array structure [17]- [18].…”

“…The two-terminal (2-T) TRAM can be one of the most promising 1T DRAM technologies for the nanoscale cross-point vertical array due to its high potential for aggressive device scaling and simple fabrication process [17]- [18]. The 2-T TRAM can modulate the energy band by using only the anode and cathode bias, which can provide an effective pathway to achieve a 4F 2 memory feature size and a 3-D stack array structure [17]- [18]. In addition, the 2-T TRAM can be fabricated in a cost-effective way due to its high compatibility with the conventional Si process and simple device structure [18].…”

“…The 2-T TRAM can modulate the energy band by using only the anode and cathode bias, which can provide an effective pathway to achieve a 4F 2 memory feature size and a 3-D stack array structure [17]- [18]. In addition, the 2-T TRAM can be fabricated in a cost-effective way due to its high compatibility with the conventional Si process and simple device structure [18]. Furthermore, a standby voltage (Vstandby) can be applied during the standby time (Tstandby) to significantly improve data retention time (Tret) because it can effectively maintain a latched state [19]- [20].…”