Design of the IBM z14 microprocessor

Jacobi, Christian; Saporito, Anthony; Recktenwald, M.; Tsai, A.; Mayer, U.; Helms, M. M.; Collura, Adam; Mak, P.; Sonnelitter, Robert; Blake, Michael A.; Bronson, T.; O'neill, Arthur; Papazova, V. K.

doi:10.1147/jrd.2018.2798718

Cited by 8 publications

(1 citation statement)

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“…IBM z15 [9,72,101] and prior system generations [10,11,17,28,50,51,80,95,96] implemented shared physical L3 caches on the processor chip, and had a separate chip that implemented a large L4 cache. The Telum design implements all of that logic in a single chip, and opts to quadruple the L2 cache to 32 MB with very low latency.…”

Section: Introductionmentioning

confidence: 99%

AI accelerator on IBM Telum processor

Lichtenau

Buyuktosunoglu²,

Bertran³

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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IBM Telum is the next generation processor chip for IBM Z and LinuxONE systems. The Telum design is focused on enterprise class workloads and it achieves over 40% per socket performance growth compared to IBM z15. The IBM Telum is the first server-class chip with a dedicated on-chip AI accelerator that enables clients to gain real time insights from their data as it is getting processed.Seamlessly infusing AI in all enterprise workloads is highly desirable to get real business insight on every transaction as well as to improve IT operation, security, and data privacy. While it would undeniably provide significant additional value, its application in practice is often accompanied by hurdles from low throughput if run on-platform to security concerns and inconsistent latency if run off-platform. The IBM Telum chip introduces an on-chip AI accelerator that provides consistent low latency and high throughput (over 200 TFLOPS in 32 chip system) inference capacity usable by all threads. The accelerator is memory coherent and directly connected to the fabric like any other general-purpose core to support low latency inference while meeting the system's transaction rate. A scalable architecture providing transparent access to AI accelerator functions via a non-privileged general-purpose core * This paper is part of the Industry Track of ISCA 2022's program.

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