The IBM z15 High Frequency Mainframe Branch Predictor Industrial Product

Adiga, N.R.; Bonanno, James; Collura, Adam; Heizmann, Matthias; Prasky, B. R.; Saporito, Anthony

doi:10.1109/isca45697.2020.00014

Cited by 11 publications

(9 citation statements)

References 9 publications

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“…Instruction cache block is fetched from the lower levels of cache hierarchy and filled in L1I ( 7 ) and the instruction is sent to the FTQ. BTB insertions and updates: For direct jump/call and conditional types of branches, we get the target in the decode stage, and we insert the target into the L1 and L2 BTBs ( 8 ). For indirect jump/call and return types of branches, we get the target after the branch is executed in the execute stage and then we update the L1 and L2 BTBs ( 8 ).…”

Section: A Designmentioning

confidence: 99%

“…BTB insertions and updates: For direct jump/call and conditional types of branches, we get the target in the decode stage, and we insert the target into the L1 and L2 BTBs ( 8 ). For indirect jump/call and return types of branches, we get the target after the branch is executed in the execute stage and then we update the L1 and L2 BTBs ( 8 ). Note that the FTQ also gets updated with the target.…”

Section: A Designmentioning

confidence: 99%

“…Recent industry trend shows that modern processors employ a decoupled front-end [5]- [8] with a multi-level BTB design. A decoupled front-end decouples the branch prediction unit from the instruction fetch and allows the branch predictor to generate the address of future instructions.…”

Section: Introductionmentioning

confidence: 99%

“…A decoupled front-end decouples the branch prediction unit from the instruction fetch and allows the branch predictor to generate the address of future instructions. Modern processors like Arm Neoverse N1 [5], AMD Zen2 [6], Samsung Exynos M3 [7] and IBM z15 [8] have high BTB capacities of 6K, 7K, 16K and 144K entries, respectively. With technology scaling slowing down [9], the number of transistors available because of reduction in transistor size is slowing down.…”

Section: Introductionmentioning

confidence: 99%

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Micro BTB: A High Performance and Lightweight Last-Level Branch Target Buffer for Servers

Gupta¹,

Panda²

2021

Preprint

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High-performance branch target buffers (BTBs) and the L1I cache are key to high-performance front-end. Modern branch predictors are highly accurate, but with an increase in code footprint in modern-day server workloads, BTB and L1I misses are still frequent. Recent industry trend shows usage of large BTBs (100s of KB per core) that provide performance closer to the ideal BTB along with a decoupled front-end that provides efficient fetch-directed L1I instruction prefetching. On the other hand, techniques proposed by academia, like BTB prefetching and using retire order stream for learning, fail to provide significant performance with modern-day processor cores that are deeper and wider.We solve the problem fundamentally by increasing the storage density of the last-level BTB. We observe that not all branch instructions require a full branch target address. Instead, we can store the branch target as a branch offset, relative to the branch instruction. Using branch offset enables the BTB to store multiple branches per entry. We reduce the BTB storage in half, but we observe that it increases skewness in the BTB. We propose a skewed indexed and compressed last-level BTB design called MicroBTB (MBTB) that stores multiple branches per BTB entry. We evaluate MBTB on 100 industry-provided server workloads. A 4K-entry MBTB provides 17.61% performance improvement compared to an 8K-entry baseline BTB design with a storage savings of 47.5KB per core.

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Section: A Designmentioning

confidence: 99%

Section: A Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Micro BTB: A High Performance and Lightweight Last-Level Branch Target Buffer for Servers

Gupta¹,

Panda²

2021

Preprint

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“…Working on the correct code path is paramount to performance since recovering from a branch misprediction and refilling the processor's instruction reservoirs (ROB, instruction/issue queue, etc.) after a pipeline restart can cost dozens of cycles [1]. Notably, as the misprediction penalty gets larger due to the increasing pipeline depth and width [19,24,30], modern processors have come to rely on incredibly accurate branch predictors.…”

Section: Introductionmentioning

confidence: 99%

Identifying and Exploiting Sparse Branch Correlations for Optimizing Branch Prediction

Zouzias¹,

Kalaitzidis²,

Berestizshevsky³

et al. 2022

Preprint

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Branch prediction is arguably one of the most important speculative mechanisms within a high-performance processor architecture. A common approach to improve branch prediction accuracy is to employ lengthy history records of previously seen branch directions to capture distant correlations between branches. The larger the history, the richer the information that the predictor can exploit for discovering predictive patterns. However, without appropriate filtering, such an approach may also heavily disorganize the predictor's internal mechanisms, leading to diminishing returns. This paper studies a fundamental control-flow property: the sparsity in the correlation between branches and recent history. First, we show that sparse branch correlations exist in standard applications and, more importantly, such correlations can be computed efficiently using sparse modeling methods. Second, we introduce a sparsity-aware branch prediction mechanism that can compactly encode and store sparse models to unlock essential performance opportunities. We evaluated our approach for various design parameters demonstrating MPKI improvements of up to 42% (2.3% on average) with 2KB of additional storage overhead. Our circuit-level evaluation of the design showed that it can operate within accepted branch prediction latencies, and under reasonable power and area limitations.

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