Design of parallel hardware neural network systems from custom analog VLSI 'building block' chips

Eberhardt,; Duong,; Thakoor,

doi:10.1109/ijcnn.1989.118697

Cited by 66 publications

(15 citation statements)

References 9 publications

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“…Others have shown that nonstochastic learning algorithms can be successfully applied with only nine bits of precision [53], and our simulations have shown that this application requires only seven or eight bits of precision (see Section VI-B). Therefore, for water vapor retrieval a neural network could be implemented with reduced complexity VLSI circuits (which are smaller and consume less power then circuits featuring 32 bits of floating-point precision), and a network could then be placed on a satellite or ground station.…”

Section: E Rbf Network Versus Cascade-correlation Networkmentioning

confidence: 88%

Execution of a remote sensing application on a custom neurocomputer

Watkins

Chau

Tawel³

et al. 1995

IEEE Trans. Neural Netw.

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A radial basis function neural network was successfully applied to an area which is relatively new for neural networks: a remote sensing application that provides estimates of water vapor content, an important parameter for climate modeling. The neural network provided results which are up to 32% better than had been previously obtained using conventional statistical methods on the same data. These results have implications for improved short-term weather forecasting and for long-term global climate modeling. The neural network approach is compared with the past and present operating algorithms at the National Oceanic and Atmospheric Administration. The radial basis function network's performance is compared with sigmoidal backpropagation network. Low-power electronic implementations of the neural methodology were explored to demonstrate the feasibility of placing the network on a remote sensing platform. This would permit processing the raw sensor data into information on the platform, eliminating the need to store the raw data, and helping to contain the expected explosion of climate data.

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Section: E Rbf Network Versus Cascade-correlation Networkmentioning

confidence: 88%

Execution of a remote sensing application on a custom neurocomputer

Watkins

Chau

Tawel³

et al. 1995

IEEE Trans. Neural Netw.

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“…VLSI implementations of ANNs usually reflect these equations, as being composed of a matrix vector multiplier followed by a non-linear activation function block. Often the multiplier and the activation function are placed on different chips to ensure cascadability and thus the ability of this chip set to implement arbitrary architectures [8]. For ease of implementation, the multiplier has usually current outputs and voltage inputs, as rows and columns in this case are added to w simply by the parallel connection of transconducting multiplying cells.…”

Section: Hardware Efficient Multiplying Dac Synapsesmentioning

confidence: 99%

Mixed analog/digital matrix-vector multiplier for neural network synapses

Lehmann

Bruun

Dietrich

1996

Analog Integr Circ Sig Process

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In this work we present a hardware efficient matrix-vector multiplier architecture for artificial neural networks with digitally stored synapse strengths. We present a novel technique for manipulating bipolar inputs based on an analog two's complements method and an accurate current rectifier/sign detector. Measurements on a CMOS test chip are presented and validates the techniques. Further, we propose to use an analog extension, based on a simple capacitive storage, for enhancing weight resolution during learning. It is shown that the implementation of Hebbian learning and back-propagation learning in this system is possible using very little additional hardware compared to the recall mode system.

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“…Among other things flexible topology [3], [12], [ l l ] , differential capacitive weights storage [4], [lo], [13], inner product multipliers [l], [2], [lo] and hyperbolic tangent activation functions [9], [ 101 have been considered. In this paper, we have combined and perturbated the existing solutions with our own work to obtain an efficient general purpose ANN in analog V L S I .…”

Section: Introduction Everal Approaches On Artificial Neural Netwomentioning

confidence: 99%

“…Thus a Kardware ANN could consist of a matrix-vector multiplier (a synapse chip) followed by a squashing function vector (a neuron chip); it turns out that this splitting of the synapses and the neurons on separate chips provides easy expandability for fully parallel systems [3], [7], (121. In this paper, we present such an analog CMOS chip set.…”

Section: Introduction Everal Approaches On Artificial Neural Netwomentioning

confidence: 99%

An analog CMOS chip set for neural networks with arbitrary topologies

Lansner

Lehmann

1993

IEEE Trans. Neural Netw.

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Abstruct-An analog CMOS chip set for implementations of artificial neural networks (ANN'S) has been fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a synapse chip. Neurons on the neuron chips can be interconnected at random via synapses on the synapse chips thus implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions which is implemented by using "parasitic" lateral bipolar transistors. The synapse test chip is a cascadable 4 x 4 matrix-vector multiplier with variable, 10 bit resolution matrix elements. The propagation delay of the test chips was measured to 2.6 ps per layer.

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Design of parallel hardware neural network systems from custom analog VLSI 'building block' chips

Cited by 66 publications

References 9 publications

Execution of a remote sensing application on a custom neurocomputer

Execution of a remote sensing application on a custom neurocomputer

Mixed analog/digital matrix-vector multiplier for neural network synapses

An analog CMOS chip set for neural networks with arbitrary topologies

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