An analog CMOS chip set for neural networks with arbitrary topologies

Lansner, John A.; Lehmann, Torsten

doi:10.1109/72.217186

Cited by 31 publications

(7 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Onchip learning has been demonstrated [14]- [19]. Some analog implementations have been very flexible [16], [20] and others have offered board-level alterability [21].…”

Section: Introductionmentioning

confidence: 99%

Toward a general-purpose analog VLSI neural network with on-chip learning

Montalvo

Gyurcsik

Paulos

1997

IEEE Trans. Neural Netw.

View full text Add to dashboard Cite

This paper describes elements necessary for a general-purpose low-cost very large scale integration (VLSI) neural network. By choosing a learning algorithm that is tolerant of analog nonidealities, the promise of high-density analog VLSI is realized. A 64-synapse, 8-neuron proof-of-concept chip is described. The synapse, which occupies only 4900 mum(2) in a 2-mum technology, includes a hybrid of nonvolatile and dynamic weight storage that provides fast and accurate learning as well as reliable long-term storage with no refreshing. The architecture is user-configurable in any one-hidden-layer topology. The user-interface is fully microprocessor compatible. Learning is accomplished with minimal external support; the user need only present inputs, targets, and a clock. Learning is fast and reliable. The chip solves four-bit parity in an average of 680 ms and is successful in about 96% of the trials.

show abstract

“…Onchip learning has been demonstrated [14]- [19]. Some analog implementations have been very flexible [16], [20] and others have offered board-level alterability [21].…”

Section: Introductionmentioning

confidence: 99%

Toward a general-purpose analog VLSI neural network with on-chip learning

Montalvo

Gyurcsik

Paulos

1997

IEEE Trans. Neural Netw.

View full text Add to dashboard Cite

show abstract

“…Categorized by storage types, there are five kinds of synapse circuits: capacitor only [1], [7]- [11], capacitor with refreshment [12]- [14], capacitor with EEPROM [4], digital [15], [16], and mixed D/A [17] circuits.…”

Section: B Synapse Circuitsmentioning

confidence: 99%

A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation

Liu

Brooke

Hirotsu

2002

IEEE Trans. Neural Netw.

View full text Add to dashboard Cite

Abstract-This paper presents a mixed signal CMOS feedforward neural-network chip with on-chip error-reduction hardware for real-time adaptation. The chip has compact on-chip weighs capable of high-speed parallel learning; the implemented learning algorithm is a genetic random search algorithm-the random weight change (RWC) algorithm. The algorithm does not require a known desired neural-network output for error calculation and is suitable for direct feedback control. With hardware experiments, we demonstrate that the RWC chip, as a direct feedback controller, successfully suppresses unstable oscillations modeling combustion engine instability in real time.Index Terms-Analog finite impulse response (FIR) filter, direct feedback control, neural-network chip, parallel on-chip learning, oscillation cancellation.

show abstract

“…22,77,115,160 In such a chip, not only the values stored in the weights of the circuit are adjustable but one can also change the connectivity of the individual units. In Ref.…”

Section: Interneuron Communicationmentioning

confidence: 99%

Neural Networks in Analog Hardware — Design and Implementation Issues

Drăghici

2000

Int. J. Neur. Syst.

View full text Add to dashboard Cite

This paper presents a brief review of some analog hardware implementations of neural networks. Several criteria for the classification of general neural networks implementations are discussed and a taxonomy induced by these criteria is presented. The paper also discusses some characteristics of analog implementations as well as some trade-offs and issues identified in the work reviewed. Parameters such as precision, chip area, power consumption, speed and noise susceptibility are discussed in the context of neural implementations. A unified review of various "VLSI friendly" algorithms is also presented. The paper concludes with some conclusions drawn from the analysis of the implementations presented.

show abstract

An analog CMOS chip set for neural networks with arbitrary topologies

Cited by 31 publications

References 11 publications

Toward a general-purpose analog VLSI neural network with on-chip learning

Toward a general-purpose analog VLSI neural network with on-chip learning

A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation

Neural Networks in Analog Hardware — Design and Implementation Issues

Contact Info

Product

Resources

About