A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation

Liu, J.; Brooke, M.A.; Hirotsu, K.

doi:10.1109/tnn.2002.1031948

Cited by 29 publications

(14 citation statements)

References 17 publications

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“…As we may know, nonlinear elements are frequently encountered in analog/digital circuit prototypes of neural networks [19,21]; involving nonlinear activation functions can be beneficial to potential design and implication. On the other hand, faster convergence is indeed required for solving GLME (1) when the linear model Complexity 3 might not satisfy increasing computational requirements.…”

Section: Theorem 1 the Neural State Matrix ( ) ∈mentioning

confidence: 99%

General Recurrent Neural Network for Solving Generalized Linear Matrix Equation

Cheng

Guo

2017

Complexity

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This brief proposes a general framework of the nonlinear recurrent neural network for solving online the generalized linear matrix equation (GLME) with global convergence property. If the linear activation function is utilized, the neural state matrix of the nonlinear recurrent neural network can globally and exponentially converge to the unique theoretical solution of GLME. Additionally, as compared with the case of using the linear activation function, two specific types of nonlinear activation functions are proposed for the general nonlinear recurrent neural network model to achieve superior convergence. Illustrative examples are shown to demonstrate the efficacy of the general nonlinear recurrent neural network model and its superior convergence when activated by the aforementioned nonlinear activation functions.

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Section: Theorem 1 the Neural State Matrix ( ) ∈mentioning

confidence: 99%

General Recurrent Neural Network for Solving Generalized Linear Matrix Equation

Cheng

Guo

2017

Complexity

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“…Given are a training set REF of n reference vectors REF= {ref 1 , ref 2 , …, ref n } and an unknown input vector IN defined in a d-dimensional space. Then, the nearest neighbor (NN) classifier, which represents a nonparametric statistical method, assigns IN to the class of its closest neighbor from the non-preprocessed REF in terms of a distance metric according to (1).…”

Section: Arg Min Refmentioning

confidence: 99%

“…Then, the nearest neighbor (NN) classifier, which represents a nonparametric statistical method, assigns IN to the class of its closest neighbor from the non-preprocessed REF in terms of a distance metric according to (1). On the other hand, IN is assigned by the KNN classifier to the class that has a majority among the k closest neighbor vectors.…”

Section: Arg Min Refmentioning

confidence: 99%

“…Accordingly, various special-purpose hardware implementtations for pattern recognition, e.g. artificial neural networks (ANNs) [1][2][3][4][5][6], support vector machines (SVMs) [7][8][9], and so on, have been proposed and significantly outperform software implementations with respect to recognition speed. Additionally, it has been proven that a hardware implementation achieves higher energy efficiency than a comparable sequential software implementation.…”

Section: Introductionmentioning

confidence: 99%

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K-Nearest Neighbor Associative Memory with Reconfigurable Word-Parallel Architecture

An¹,

Mihara²,

Yamasaki³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vectorcomponent parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 nm CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 mW and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 MHz and 1.8 V).

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“…The PRWC training algorithm is "model-free" such as Random Weight Change (RWC) [5], Weight Perturbation (WP) [6] and Simulated Annealing (SA) [8]. In the comparison with the GD on-line algorithm, the PRWC algorithm results in further simplifcation in circuit design as it does not require intermediate network outputs.…”

Section: B Probabilistic Random Weight Change (Prwc)mentioning

confidence: 99%

Local Cluster Neural Network On-chip Training

Zhang

Sitte

2006

The 2006 IEEE International Joint Conference on Neural Network Proceedings

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Abstract-The local cluster neural network is a feedforward RBF network that has been implemented in analogue neural net chip. The LCNN chip can be trained by chip-in-theloop training and this training method has been demonstrated to work efficiently. In order to increase the functionality of LCNN chip, we proposed on-chip training for the LCNN chip. In this paper, we describe two training algorithmsGradient Descent and Probabilistic Random Weight Change, which are used in LCNN on-chip training simulations. We also present the experiment results from the simulations in multidimensional function approximation. The training convergence is investigated and analyzed. The circuite signal flow chart for these two algorithms are designed.

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A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation

Cited by 29 publications

References 17 publications

General Recurrent Neural Network for Solving Generalized Linear Matrix Equation

General Recurrent Neural Network for Solving Generalized Linear Matrix Equation

K-Nearest Neighbor Associative Memory with Reconfigurable Word-Parallel Architecture

Local Cluster Neural Network On-chip Training

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